From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vikas Manocha Date: Mon, 27 Mar 2017 13:02:45 -0700 Subject: [U-Boot] [PATCH v4 2/2] stm32f7: enable instruction & data cache In-Reply-To: <1490644970-19266-1-git-send-email-vikas.manocha@st.com> References: <1490644970-19266-1-git-send-email-vikas.manocha@st.com> Message-ID: <1490644970-19266-3-git-send-email-vikas.manocha@st.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de It also enables commands for cache enable/disable/status. Signed-off-by: Vikas Manocha cc: Christophe KERELLO --- Changed in v4: None Changed in v3: None Changed in v2: None arch/arm/mach-stm32/stm32f7/soc.c | 2 ++ include/configs/stm32f746-disco.h | 4 +--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c index 06af631..6f9704a 100644 --- a/arch/arm/mach-stm32/stm32f7/soc.c +++ b/arch/arm/mach-stm32/stm32f7/soc.c @@ -58,6 +58,8 @@ int arch_cpu_init(void) (V7M_MPU_RASR_XN_ENABLE | V7M_MPU_RASR_AP_RW_RW | 0x01 << V7M_MPU_RASR_TEX_SHIFT + | 0x01 << V7M_MPU_RASR_B_SHIFT + | 0x01 << V7M_MPU_RASR_C_SHIFT | V7M_MPU_RASR_SIZE_8MB | V7M_MPU_RASR_EN) , &V7M_MPU->rasr diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index ae3211a..9e9406a 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -14,9 +14,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 #define CONFIG_SYS_TEXT_BASE 0x08000000 -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF - /* * Configuration of the external SDRAM memory */ @@ -82,4 +79,5 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_CMD_MEM +#define CONFIG_CMD_CACHE #endif /* __CONFIG_H */ -- 1.9.1