[U-Boot] [PATCH 0/5] Add support for NAND flash to A7K/A8K SoC family

[U-Boot] [PATCH 0/5] Add support for NAND flash to A7K/A8K SoC family

[kostap at marvell.com]

From: Konstantin Porotchkin <kostap@marvell.com>

This patch series adds NAND flash support to Marvell A7K/A8K SoC families.
Additionally it fixes the pxa3xx driver by enforcing usage of DTS-supplied
NAND parameters instead of using the hardcoded ones.
The Marvell "bubt" command code related to NAND flash is updated according
to new DM driver APIs.
Added a default configuration file for Armada-7040 DB with NAND flash
selected as a boot device instead of default SPI flash.
Added a DTS file for this setup that includes proper MPPs configuration.

These patches should be applied on top of the following patch that was sent
to the u-boot list earlier:
"fix: nand: Fix nand RW access wrappers"

Konstantin Porotchkin (5):
  fix: nand: pxa3xx: Remove hardcode values from the driver
  arm64: mvebu: a8k: Add support for NAND clock get
  arm64: mvebu: Fix the bubt comamnd NAND device support
  arm64: a8k: dts: Add support for NAND devices on A8K platform
  arm64: mvebu: a8k: Add NAND configuration parameters

 arch/arm/dts/Makefile                   |   1 +
 arch/arm/dts/armada-7040-db-nand.dts    | 222 ++++++++++++++++++++++++++++++++
 arch/arm/dts/armada-7040-db.dts         |   1 +
 arch/arm/dts/armada-cp110-master.dtsi   |  13 ++
 arch/arm/mach-mvebu/armada8k/cpu.c      |  16 +++
 cmd/mvebu/bubt.c                        |  13 +-
 configs/mvebu_db-88f7040-nand_defconfig |  72 +++++++++++
 drivers/mtd/nand/pxa3xx_nand.c          |  62 +++++++--
 include/configs/mvebu_armada-8k.h       |  11 ++
 9 files changed, 397 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/dts/armada-7040-db-nand.dts
 create mode 100644 configs/mvebu_db-88f7040-nand_defconfig

-- 
2.7.4

[U-Boot] [PATCH 1/5] fix: nand: pxa3xx: Remove hardcode values from the driver

[kostap at marvell.com]

From: Konstantin Porotchkin <kostap@marvell.com>

Obtain NAND controller setup parameters from the device
tree instead of using hardcoded values.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Scott Wood <oss@buserror.net>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c | 62 ++++++++++++++++++++++++++++++++++++------
 1 file changed, 54 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index dfe8966..0042a7b 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <malloc.h>
+#include <fdtdec.h>
 #include <nand.h>
 #include <linux/errno.h>
 #include <asm/io.h>
@@ -19,6 +20,8 @@
 
 #include "pxa3xx_nand.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define TIMEOUT_DRAIN_FIFO	5	/* in ms */
 #define	CHIP_DELAY_TIMEOUT	200
 #define NAND_STOP_DELAY		40
@@ -1510,8 +1513,6 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info)
 		chip->cmdfunc		= nand_cmdfunc;
 	}
 
-	info->mmio_base = (void __iomem *)MVEBU_NAND_BASE;
-
 	/* Allocate a buffer to allow flash detection */
 	info->buf_size = INIT_BUFFER_SIZE;
 	info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
@@ -1533,17 +1534,62 @@ fail_disable_clk:
 static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
 {
 	struct pxa3xx_nand_platform_data *pdata;
+	const void *blob = gd->fdt_blob;
+	int node = -1;
 
 	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 	if (!pdata)
 		return -ENOMEM;
 
-	pdata->enable_arbiter = 1;
-	pdata->num_cs = 1;
+	/* Get address decoding nodes from the FDT blob */
+	do {
+		node = fdt_node_offset_by_compatible(blob, node,
+						     "marvell,mvebu-pxa3xx-nand");
+		if (node < 0)
+			break;
+
+		/* Bypass disabeld nodes */
+		if (!fdtdec_get_is_enabled(blob, node))
+			continue;
 
-	info->pdata = pdata;
+		/* Get the first enabled NAND controler base address */
+		info->mmio_base =
+			(void __iomem *)fdtdec_get_addr_size_auto_noparent(
+					blob, node, "reg", 0, NULL, true);
 
-	return 0;
+		pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1);
+		if (pdata->num_cs != 1) {
+			error("pxa3xx driver supports single CS only\n");
+			break;
+		}
+
+		if (fdtdec_get_bool(blob, node, "nand-enable-arbiter"))
+			pdata->enable_arbiter = 1;
+
+		if (fdtdec_get_bool(blob, node, "nand-keep-config"))
+			pdata->keep_config = 1;
+
+		/*
+		 * ECC parameters.
+		 * If these are not set, they will be selected according
+		 * to the detected flash type.
+		 */
+		/* ECC strength */
+		pdata->ecc_strength = fdtdec_get_int(blob, node,
+						     "nand-ecc-strength", 0);
+
+		/* ECC step size */
+		pdata->ecc_step_size = fdtdec_get_int(blob, node,
+						      "nand-ecc-step-size", 0);
+
+		info->pdata = pdata;
+
+		/* Currently support only a single NAND controller */
+		return 0;
+
+	} while (node >= 0);
+
+	return -EINVAL;
 }
 
 static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
@@ -1603,8 +1649,8 @@ void board_nand_init(void)
 	int ret;
 
 	info = kzalloc(sizeof(*info) +
-				sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
-			GFP_KERNEL);
+		       sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
+		       GFP_KERNEL);
 	if (!info)
 		return;
 
-- 
2.7.4

[U-Boot] [PATCH 2/5] arm64: mvebu: a8k: Add support for NAND clock get

[kostap at marvell.com]

From: Konstantin Porotchkin <kostap@marvell.com>

Implement mvebu_get_nand_clock call for A8K family.
This function is used by PXA3XX NAND driver.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
---
 arch/arm/mach-mvebu/armada8k/cpu.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c
index 2325e9a..e18ca6b 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -110,3 +110,19 @@ void reset_cpu(ulong ignored)
 	reg &= ~(1 << RFU_SW_RESET_OFFSET);
 	writel(reg, RFU_GLOBAL_SW_RST);
 }
+
+#ifdef CONFIG_NAND_PXA3XX
+/* Return NAND clock in Hz */
+u32 mvebu_get_nand_clock(void)
+{
+	unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
+	unsigned long NF_CLOCK_SEL_MASK = 0x1;
+	u32 reg;
+
+	reg = readl(NAND_FLASH_CLK_CTRL);
+	if (reg & NF_CLOCK_SEL_MASK)
+		return 400 * 1000000;
+	else
+		return 250 * 1000000;
+}
+#endif
-- 
2.7.4

[U-Boot] [PATCH 3/5] arm64: mvebu: Fix the bubt comamnd NAND device support

[kostap at marvell.com]

From: Konstantin Porotchkin <kostap@marvell.com>

Fix the NAND structures in bubt command according to latest
changes in MTD API.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
---
 cmd/mvebu/bubt.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index b752927..1e1f0af 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -309,16 +309,17 @@ static int is_spi_active(void)
 #ifdef CONFIG_CMD_NAND
 static int nand_burn_image(size_t image_size)
 {
-	int ret, block_size;
-	nand_info_t *nand;
+	int ret;
+	uint32_t block_size;
+	struct mtd_info *nand;
 	int dev = nand_curr_device;
 
 	if ((dev < 0) || (dev >= CONFIG_SYS_MAX_NAND_DEVICE) ||
-	    (!nand_info[dev].name)) {
+	    (!nand_info[dev]->name)) {
 		puts("\nno devices available\n");
 		return -ENOMEDIUM;
 	}
-	nand = &nand_info[dev];
+	nand = nand_info[dev];
 	block_size = nand->erasesize;
 
 	/* Align U-Boot size to currently used blocksize */
@@ -334,8 +335,8 @@ static int nand_burn_image(size_t image_size)
 	printf("Done!\n");
 
 	/* Write the image to flash */
-	printf("Writing image:...");
-	printf("&image_size = 0x%p\n", (void *)&image_size);
+	printf("Writing %d bytes from 0x%lx to offset 0 ... ",
+	       (int)image_size, get_load_addr());
 	ret = nand_write(nand, 0, &image_size, (void *)get_load_addr());
 	if (ret)
 		printf("Error!\n");
-- 
2.7.4

[U-Boot] [PATCH 4/5] arm64: a8k: dts: Add support for NAND devices on A8K platform

[kostap at marvell.com]

From: Konstantin Porotchkin <kostap@marvell.com>

Add NAND to CP master device tree. Add armada-7040-db-nand
device tree for the board configured with NAND boot device.
Add comment about boot device ID to armada-7040-db DTS.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
---
 arch/arm/dts/Makefile                 |   1 +
 arch/arm/dts/armada-7040-db-nand.dts  | 222 ++++++++++++++++++++++++++++++++++
 arch/arm/dts/armada-7040-db.dts       |   1 +
 arch/arm/dts/armada-cp110-master.dtsi |  13 ++
 4 files changed, 237 insertions(+)
 create mode 100644 arch/arm/dts/armada-7040-db-nand.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0fbbb9b..d09d8f2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-388-gp.dtb			\
 	armada-385-amc.dtb			\
 	armada-7040-db.dtb			\
+	armada-7040-db-nand.dtb			\
 	armada-8040-db.dtb			\
 	armada-8040-mcbin.dtb			\
 	armada-xp-gp.dtb			\
diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts
new file mode 100644
index 0000000..da213ea
--- /dev/null
+++ b/arch/arm/dts/armada-7040-db-nand.dts
@@ -0,0 +1,222 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada 7040 Development board platform
+ * Boot device: NAND, 0xE (SW3)
+ */
+
+#include "armada-7040.dtsi"
+
+/ {
+	model = "Marvell Armada 7040 DB board";
+	compatible = "marvell,armada7040-db", "marvell,armada7040",
+		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cpm_i2c0;
+		spi0 = &cpm_spi1;
+	};
+
+	memory at 00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&ap_pinctl {
+	   /* MPP Bus:
+	    * SDIO  [0-5]
+	    * UART0 [11,19]
+	    */
+		  /* 0   1   2   3   4   5   6   7   8   9 */
+	pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
+		     0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+
+&cpm_pcie2 {
+	status = "okay";
+};
+
+&cpm_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+&cpm_pinctl {
+		/* MPP Bus:
+		 * AUDIO   [0-5]
+                 * GBE     [6-11]
+		 * SS_PWDN [12]
+		 * NF_RBn  [13]
+                 * GPIO    [14]
+		 * DEV_BUS [15-27]
+		 * SATA1   [28]
+		 * UART0   [29-30]
+		 * MSS_VTT_EN [31]
+		 * SMI	   [32,34]
+		 * XSMI    [35-36]
+		 * I2C	   [37-38]
+		 * RGMII1  [44-55]
+		 * SD	   [56-61]
+		 * GPIO    [62]
+		 */
+		 /*   0   1   2   3   4   5   6   7   8   9 */
+	 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
+		      0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
+		      0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa
+		      0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
+		      0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1
+		      0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
+		      0xe 0xe 0x0>;
+};
+
+&cpm_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_spi0_pins>;
+	status = "disabled";
+
+	spi-flash at 0 {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <20000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition at 0 {
+				label = "U-Boot";
+				reg = <0x0 0x200000>;
+			};
+
+			partition at 400000 {
+				label = "Filesystem";
+				reg = <0x200000 0xe00000>;
+			};
+		};
+	};
+};
+
+&cpm_sata0 {
+	status = "okay";
+};
+
+&cpm_usb3_0 {
+	status = "okay";
+};
+
+&cpm_usb3_1 {
+	status = "okay";
+};
+
+&cpm_comphy {
+	phy0 {
+		phy-type = <PHY_TYPE_SGMII2>;
+		phy-speed = <PHY_SPEED_3_125G>;
+	};
+
+	phy1 {
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy2 {
+		phy-type = <PHY_TYPE_SGMII0>;
+		phy-speed = <PHY_SPEED_1_25G>;
+	};
+
+	phy3 {
+		phy-type = <PHY_TYPE_SATA1>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy4 {
+		phy-type = <PHY_TYPE_USB3_HOST1>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy5 {
+		phy-type = <PHY_TYPE_PEX2>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+};
+
+&cpm_nand {
+	status = "okay";
+};
+
+&cpm_utmi0 {
+	status = "okay";
+};
+
+&cpm_utmi1 {
+	status = "okay";
+};
+
+&ap_sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+};
+
+&cpm_sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+};
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 63442df..3bd699d 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -42,6 +42,7 @@
 
 /*
  * Device Tree file for Marvell Armada 7040 Development board platform
+ * Boot device: SPI NOR, 0x32 (SW3)
  */
 
 #include "armada-7040.dtsi"
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
index 1f0edde..d4c6cc6 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -236,6 +236,19 @@
 				dma-coherent;
 				status = "disabled";
 			};
+			cpm_nand: nand at 720000 {
+				compatible = "marvell,mvebu-pxa3xx-nand";
+				reg = <0x720000 0x100>;
+				#address-cells = <1>;
+
+				clocks = <&cpm_syscon0 1 2>;
+				nand-enable-arbiter;
+				num-cs = <1>;
+				nand-ecc-strength = <4>;
+				nand-ecc-step-size = <512>;
+				status = "disabled";
+			};
+
 		};
 
 		cpm_pcie0: pcie at f2600000 {
-- 
2.7.4

[U-Boot] [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration parameters

[kostap at marvell.com]

From: Konstantin Porotchkin <kostap@marvell.com>

Add NAND configuration parameters to A8K shared config file.
Add defconfig for db-88f7040 board with boot from NAND setup.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
---
 configs/mvebu_db-88f7040-nand_defconfig | 72 +++++++++++++++++++++++++++++++++
 include/configs/mvebu_armada-8k.h       | 11 +++++
 2 files changed, 83 insertions(+)
 create mode 100644 configs/mvebu_db-88f7040-nand_defconfig

diff --git a/configs/mvebu_db-88f7040-nand_defconfig b/configs/mvebu_db-88f7040-nand_defconfig
new file mode 100644
index 0000000..d86c18e
--- /dev/null
+++ b/configs/mvebu_db-88f7040-nand_defconfig
@@ -0,0 +1,72 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MVEBU_ARMADA_8K=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db-nand"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_BLOCK_CACHE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MVEBU_NAND_BOOT=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_PHYLIB=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index a8a9d15..839abd9 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -76,11 +76,22 @@
 #define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
 
 /* Environment in SPI NOR flash */
+#ifdef CONFIG_MVEBU_SPI_BOOT
 #define CONFIG_ENV_IS_IN_SPI_FLASH
+/* Environment in NAND flash */
+#elif defined(CONFIG_MVEBU_NAND_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#endif
+
 #define CONFIG_ENV_OFFSET		0x180000 /* as Marvell U-Boot version */
 #define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
 #define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
 
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
 /* USB 2.0 */
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 
-- 
2.7.4

[U-Boot] [PATCH 2/5] arm64: mvebu: a8k: Add support for NAND clock get

[Stefan Roese]

On 28.03.2017 17:16, kostap at marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Implement mvebu_get_nand_clock call for A8K family.
> This function is used by PXA3XX NAND driver.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Igal Liberman <igall@marvell.com>
> Cc: Nadav Haklai <nadavh@marvell.com>
> ---
>  arch/arm/mach-mvebu/armada8k/cpu.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c
> index 2325e9a..e18ca6b 100644
> --- a/arch/arm/mach-mvebu/armada8k/cpu.c
> +++ b/arch/arm/mach-mvebu/armada8k/cpu.c
> @@ -110,3 +110,19 @@ void reset_cpu(ulong ignored)
>  	reg &= ~(1 << RFU_SW_RESET_OFFSET);
>  	writel(reg, RFU_GLOBAL_SW_RST);
>  }
> +
> +#ifdef CONFIG_NAND_PXA3XX

Do we really need to have this code conditionally compiled here?

> +/* Return NAND clock in Hz */
> +u32 mvebu_get_nand_clock(void)
> +{
> +	unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;

I know that some of this code is historically done this way. But
with DT available now, isn't it possible to at least get the base
address of such registers from the DT instead of hardcoding it?

Thanks,
Stefan

[U-Boot] [PATCH 4/5] arm64: a8k: dts: Add support for NAND devices on A8K platform

[Stefan Roese]

On 28.03.2017 17:16, kostap at marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Add NAND to CP master device tree. Add armada-7040-db-nand
> device tree for the board configured with NAND boot device.
> Add comment about boot device ID to armada-7040-db DTS.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Igal Liberman <igall@marvell.com>
> Cc: Nadav Haklai <nadavh@marvell.com>
> ---
>  arch/arm/dts/Makefile                 |   1 +
>  arch/arm/dts/armada-7040-db-nand.dts  | 222 ++++++++++++++++++++++++++++++++++
>  arch/arm/dts/armada-7040-db.dts       |   1 +
>  arch/arm/dts/armada-cp110-master.dtsi |  13 ++
>  4 files changed, 237 insertions(+)
>  create mode 100644 arch/arm/dts/armada-7040-db-nand.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0fbbb9b..d09d8f2 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
>  	armada-388-gp.dtb			\
>  	armada-385-amc.dtb			\
>  	armada-7040-db.dtb			\
> +	armada-7040-db-nand.dtb			\
>  	armada-8040-db.dtb			\
>  	armada-8040-mcbin.dtb			\
>  	armada-xp-gp.dtb			\
> diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts
> new file mode 100644
> index 0000000..da213ea
> --- /dev/null
> +++ b/arch/arm/dts/armada-7040-db-nand.dts
> @@ -0,0 +1,222 @@
> +/*
> + * Copyright (C) 2017 Marvell Technology Group Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This library is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/*
> + * Device Tree file for Marvell Armada 7040 Development board platform
> + * Boot device: NAND, 0xE (SW3)
> + */
> +
> +#include "armada-7040.dtsi"
> +
> +/ {
> +	model = "Marvell Armada 7040 DB board";

Perhaps a comment here mentioning NAND as well?

> +	compatible = "marvell,armada7040-db", "marvell,armada7040",
> +		     "marvell,armada-ap806-quad", "marvell,armada-ap806";

So this is identical to the original 7040-db board? Perhaps its
better (or even necessary) to add a new "NAND" specific
compatible string here?

> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	aliases {
> +		i2c0 = &cpm_i2c0;
> +		spi0 = &cpm_spi1;
> +	};
> +
> +	memory at 00000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x0 0x0 0x80000000>;
> +	};
> +};
> +
> +&ap_pinctl {
> +	   /* MPP Bus:
> +	    * SDIO  [0-5]
> +	    * UART0 [11,19]
> +	    */
> +		  /* 0   1   2   3   4   5   6   7   8   9 */
> +	pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
> +		     0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +
> +&cpm_pcie2 {
> +	status = "okay";
> +};
> +
> +&cpm_i2c0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cpm_i2c0_pins>;
> +	status = "okay";
> +	clock-frequency = <100000>;
> +};
> +
> +&cpm_pinctl {
> +		/* MPP Bus:
> +		 * AUDIO   [0-5]
> +                 * GBE     [6-11]
> +		 * SS_PWDN [12]
> +		 * NF_RBn  [13]
> +                 * GPIO    [14]
> +		 * DEV_BUS [15-27]
> +		 * SATA1   [28]
> +		 * UART0   [29-30]
> +		 * MSS_VTT_EN [31]
> +		 * SMI	   [32,34]
> +		 * XSMI    [35-36]
> +		 * I2C	   [37-38]
> +		 * RGMII1  [44-55]
> +		 * SD	   [56-61]
> +		 * GPIO    [62]
> +		 */

The indentation looks "fishy" above.

> +		 /*   0   1   2   3   4   5   6   7   8   9 */
> +	 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
> +		      0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
> +		      0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa
> +		      0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
> +		      0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1
> +		      0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
> +		      0xe 0xe 0x0>;
> +};
> +
> +&cpm_spi1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cpm_spi0_pins>;
> +	status = "disabled";
> +
> +	spi-flash at 0 {
> +		#address-cells = <0x1>;
> +		#size-cells = <0x1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0x0>;
> +		spi-max-frequency = <20000000>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition at 0 {
> +				label = "U-Boot";
> +				reg = <0x0 0x200000>;
> +			};
> +
> +			partition at 400000 {
> +				label = "Filesystem";
> +				reg = <0x200000 0xe00000>;
> +			};
> +		};
> +	};
> +};
> +
> +&cpm_sata0 {
> +	status = "okay";
> +};
> +
> +&cpm_usb3_0 {
> +	status = "okay";
> +};
> +
> +&cpm_usb3_1 {
> +	status = "okay";
> +};
> +
> +&cpm_comphy {
> +	phy0 {
> +		phy-type = <PHY_TYPE_SGMII2>;
> +		phy-speed = <PHY_SPEED_3_125G>;
> +	};
> +
> +	phy1 {
> +		phy-type = <PHY_TYPE_USB3_HOST0>;
> +		phy-speed = <PHY_SPEED_5G>;
> +	};
> +
> +	phy2 {
> +		phy-type = <PHY_TYPE_SGMII0>;
> +		phy-speed = <PHY_SPEED_1_25G>;
> +	};
> +
> +	phy3 {
> +		phy-type = <PHY_TYPE_SATA1>;
> +		phy-speed = <PHY_SPEED_5G>;
> +	};
> +
> +	phy4 {
> +		phy-type = <PHY_TYPE_USB3_HOST1>;
> +		phy-speed = <PHY_SPEED_5G>;
> +	};
> +
> +	phy5 {
> +		phy-type = <PHY_TYPE_PEX2>;
> +		phy-speed = <PHY_SPEED_5G>;
> +	};
> +};
> +
> +&cpm_nand {
> +	status = "okay";
> +};
> +
> +&cpm_utmi0 {
> +	status = "okay";
> +};
> +
> +&cpm_utmi1 {
> +	status = "okay";
> +};
> +
> +&ap_sdhci0 {
> +	status = "okay";
> +	bus-width = <4>;
> +	no-1-8-v;
> +	non-removable;
> +};
> +
> +&cpm_sdhci0 {
> +	status = "okay";
> +	bus-width = <4>;
> +	no-1-8-v;
> +	non-removable;
> +};
> diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
> index 63442df..3bd699d 100644
> --- a/arch/arm/dts/armada-7040-db.dts
> +++ b/arch/arm/dts/armada-7040-db.dts
> @@ -42,6 +42,7 @@
>
>  /*
>   * Device Tree file for Marvell Armada 7040 Development board platform
> + * Boot device: SPI NOR, 0x32 (SW3)
>   */
>
>  #include "armada-7040.dtsi"
> diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
> index 1f0edde..d4c6cc6 100644
> --- a/arch/arm/dts/armada-cp110-master.dtsi
> +++ b/arch/arm/dts/armada-cp110-master.dtsi
> @@ -236,6 +236,19 @@
>  				dma-coherent;
>  				status = "disabled";
>  			};
> +			cpm_nand: nand at 720000 {
> +				compatible = "marvell,mvebu-pxa3xx-nand";
> +				reg = <0x720000 0x100>;
> +				#address-cells = <1>;
> +
> +				clocks = <&cpm_syscon0 1 2>;
> +				nand-enable-arbiter;
> +				num-cs = <1>;
> +				nand-ecc-strength = <4>;
> +				nand-ecc-step-size = <512>;
> +				status = "disabled";
> +			};
> +

This empty line should probably be added before the "cpm_nand"
node.

Thanks,
Stefan

[U-Boot] [PATCH 2/5] arm64: mvebu: a8k: Add support for NAND clock get

[Konstantin Porotchkin]

Hi, Stefan,

On 03/30/2017 04:15 PM, Stefan Roese wrote:
> On 28.03.2017 17:16, kostap at marvell.com wrote:
>> From: Konstantin Porotchkin <kostap@marvell.com>
>>
>> Implement mvebu_get_nand_clock call for A8K family.
>> This function is used by PXA3XX NAND driver.
>>
>> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
>> Cc: Stefan Roese <sr@denx.de>
>> Cc: Igal Liberman <igall@marvell.com>
>> Cc: Nadav Haklai <nadavh@marvell.com>
>> ---
>>  arch/arm/mach-mvebu/armada8k/cpu.c | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c
>> b/arch/arm/mach-mvebu/armada8k/cpu.c
>> index 2325e9a..e18ca6b 100644
>> --- a/arch/arm/mach-mvebu/armada8k/cpu.c
>> +++ b/arch/arm/mach-mvebu/armada8k/cpu.c
>> @@ -110,3 +110,19 @@ void reset_cpu(ulong ignored)
>>      reg &= ~(1 << RFU_SW_RESET_OFFSET);
>>      writel(reg, RFU_GLOBAL_SW_RST);
>>  }
>> +
>> +#ifdef CONFIG_NAND_PXA3XX
>
> Do we really need to have this code conditionally compiled here?
I can remove it, just wanted not to increase the code size if not 
needed. Do you think it is excessive?
>
>> +/* Return NAND clock in Hz */
>> +u32 mvebu_get_nand_clock(void)
>> +{
>> +    unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
>
> I know that some of this code is historically done this way. But
> with DT available now, isn't it possible to at least get the base
> address of such registers from the DT instead of hardcoding it?
I see what you saying and I agree it is not as elegant as it could be. 
The only problem is that the NAND clock register is not part of the SoC 
NAND unit, so the IO base taken from DTS entry for NAND device is not 
really useful here. NAND unit and its clock configuration register are 
only sharing the CP0 base - 0xF2000000.

>
> Thanks,
> Stefan

[U-Boot] [PATCH 2/5] arm64: mvebu: a8k: Add support for NAND clock get

[Stefan Roese]

Hi Kosta,

On 30.03.2017 17:46, Konstantin Porotchkin wrote:
> On 03/30/2017 04:15 PM, Stefan Roese wrote:
>> On 28.03.2017 17:16, kostap at marvell.com wrote:
>>> From: Konstantin Porotchkin <kostap@marvell.com>
>>>
>>> Implement mvebu_get_nand_clock call for A8K family.
>>> This function is used by PXA3XX NAND driver.
>>>
>>> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
>>> Cc: Stefan Roese <sr@denx.de>
>>> Cc: Igal Liberman <igall@marvell.com>
>>> Cc: Nadav Haklai <nadavh@marvell.com>
>>> ---
>>>  arch/arm/mach-mvebu/armada8k/cpu.c | 16 ++++++++++++++++
>>>  1 file changed, 16 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c
>>> b/arch/arm/mach-mvebu/armada8k/cpu.c
>>> index 2325e9a..e18ca6b 100644
>>> --- a/arch/arm/mach-mvebu/armada8k/cpu.c
>>> +++ b/arch/arm/mach-mvebu/armada8k/cpu.c
>>> @@ -110,3 +110,19 @@ void reset_cpu(ulong ignored)
>>>      reg &= ~(1 << RFU_SW_RESET_OFFSET);
>>>      writel(reg, RFU_GLOBAL_SW_RST);
>>>  }
>>> +
>>> +#ifdef CONFIG_NAND_PXA3XX
>>
>> Do we really need to have this code conditionally compiled here?
> I can remove it, just wanted not to increase the code size if not
> needed. Do you think it is excessive?

Yes, please remove it. These platforms are not that size constraint
as some SPL ones are. The pros for not adding more #ifdef's
overweight the small code size increase - at least for my taste.

>>> +/* Return NAND clock in Hz */
>>> +u32 mvebu_get_nand_clock(void)
>>> +{
>>> +    unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
>>
>> I know that some of this code is historically done this way. But
>> with DT available now, isn't it possible to at least get the base
>> address of such registers from the DT instead of hardcoding it?
> I see what you saying and I agree it is not as elegant as it could be.
> The only problem is that the NAND clock register is not part of the SoC
> NAND unit, so the IO base taken from DTS entry for NAND device is not
> really useful here. NAND unit and its clock configuration register are
> only sharing the CP0 base - 0xF2000000.

Right. I wouldn't have expected that this register is located
in the NAND controller space - more likely some clocking controller
/ infrastructure. I'm okay with this patch for now, but perhaps
you could add a small "ToDo" comment here, that this should be
converted at some time, once a mvebu / a7k/8K DM clock driver
is available in U-Boot (see drivers/clk)?

Thanks,
Stefan

[U-Boot] [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration parameters

[Stefan Roese]

Hi Kosta,

On 28.03.2017 17:16, kostap at marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
> 
> Add NAND configuration parameters to A8K shared config file.
> Add defconfig for db-88f7040 board with boot from NAND setup.
> 
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Igal Liberman <igall@marvell.com>
> Cc: Nadav Haklai <nadavh@marvell.com>
> ---
>  configs/mvebu_db-88f7040-nand_defconfig | 72 +++++++++++++++++++++++++++++++++
>  include/configs/mvebu_armada-8k.h       | 11 +++++
>  2 files changed, 83 insertions(+)
>  create mode 100644 configs/mvebu_db-88f7040-nand_defconfig

I'm currently testing this patchset and get this compilation error
via Travis:

   aarch64:  +   mvebu_db-88f7040-nand
+drivers/mtd/nand/pxa3xx_nand.c: In function alloc_nand_resource:
+drivers/mtd/nand/pxa3xx_nand.c:1513:36: error: MVEBU_NAND_BASE undeclared (first use in this function)
+  info->mmio_base = (void __iomem *)MVEBU_NAND_BASE;

Did I miss a patch that adds this macro for A7/8k?

Thanks,
Stefan

[U-Boot] [EXT] Re: [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration parameters

[Kostya Porotchkin]

Hi, Stefan,

> -----Original Message-----
> From: Stefan Roese [mailto:sr at denx.de]
> Sent: Wednesday, April 19, 2017 11:45
> To: Kostya Porotchkin; u-boot at lists.denx.de
> Cc: Igal Liberman; Nadav Haklai
> Subject: [EXT] Re: [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration
> parameters
> 
> External Email
> 
> ----------------------------------------------------------------------
> Hi Kosta,
> 
> On 28.03.2017 17:16, kostap at marvell.com wrote:
> > From: Konstantin Porotchkin <kostap@marvell.com>
> >
> > Add NAND configuration parameters to A8K shared config file.
> > Add defconfig for db-88f7040 board with boot from NAND setup.
> >
> > Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> > Cc: Stefan Roese <sr@denx.de>
> > Cc: Igal Liberman <igall@marvell.com>
> > Cc: Nadav Haklai <nadavh@marvell.com>
> > ---
> >  configs/mvebu_db-88f7040-nand_defconfig | 72
> +++++++++++++++++++++++++++++++++
> >  include/configs/mvebu_armada-8k.h       | 11 +++++
> >  2 files changed, 83 insertions(+)
> >  create mode 100644 configs/mvebu_db-88f7040-nand_defconfig
> 
> I'm currently testing this patchset and get this compilation error via
> Travis:
> 
>    aarch64:  +   mvebu_db-88f7040-nand
> +drivers/mtd/nand/pxa3xx_nand.c: In function alloc_nand_resource:
> +drivers/mtd/nand/pxa3xx_nand.c:1513:36: error: MVEBU_NAND_BASE
> +undeclared (first use in this function)
> +  info->mmio_base = (void __iomem *)MVEBU_NAND_BASE;
> 
> Did I miss a patch that adds this macro for A7/8k?
[Konstantin Porotchkin] 
The hardcoded values should be changed in the following patch:
[PATCH 1/5] fix: nand: pxa3xx: Remove hardcode values from the driver
However I do not see it on patchworks site.
Should I re-send it?

Thanks
Kosta
> 
> Thanks,
> Stefan

[U-Boot] [EXT] Re: [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration parameters

[Stefan Roese]

Hi Kosta,

On 19.04.2017 10:50, Kostya Porotchkin wrote:
> Hi, Stefan,
>
>> -----Original Message-----
>> From: Stefan Roese [mailto:sr at denx.de]
>> Sent: Wednesday, April 19, 2017 11:45
>> To: Kostya Porotchkin; u-boot at lists.denx.de
>> Cc: Igal Liberman; Nadav Haklai
>> Subject: [EXT] Re: [PATCH 5/5] arm64: mvebu: a8k: Add NAND configuration
>> parameters
>>
>> External Email
>>
>> ----------------------------------------------------------------------
>> Hi Kosta,
>>
>> On 28.03.2017 17:16, kostap at marvell.com wrote:
>>> From: Konstantin Porotchkin <kostap@marvell.com>
>>>
>>> Add NAND configuration parameters to A8K shared config file.
>>> Add defconfig for db-88f7040 board with boot from NAND setup.
>>>
>>> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
>>> Cc: Stefan Roese <sr@denx.de>
>>> Cc: Igal Liberman <igall@marvell.com>
>>> Cc: Nadav Haklai <nadavh@marvell.com>
>>> ---
>>>  configs/mvebu_db-88f7040-nand_defconfig | 72
>> +++++++++++++++++++++++++++++++++
>>>  include/configs/mvebu_armada-8k.h       | 11 +++++
>>>  2 files changed, 83 insertions(+)
>>>  create mode 100644 configs/mvebu_db-88f7040-nand_defconfig
>>
>> I'm currently testing this patchset and get this compilation error via
>> Travis:
>>
>>    aarch64:  +   mvebu_db-88f7040-nand
>> +drivers/mtd/nand/pxa3xx_nand.c: In function alloc_nand_resource:
>> +drivers/mtd/nand/pxa3xx_nand.c:1513:36: error: MVEBU_NAND_BASE
>> +undeclared (first use in this function)
>> +  info->mmio_base = (void __iomem *)MVEBU_NAND_BASE;
>>
>> Did I miss a patch that adds this macro for A7/8k?
> [Konstantin Porotchkin]
> The hardcoded values should be changed in the following patch:
> [PATCH 1/5] fix: nand: pxa3xx: Remove hardcode values from the driver
> However I do not see it on patchworks site.
> Should I re-send it?

No need. I've found it in my inbox. Travis build is already restarted...

Thanks,
Stefan

[U-Boot] [PATCH 3/5] arm64: mvebu: Fix the bubt comamnd NAND device support

[Stefan Roese]

On 28.03.2017 17:16, kostap at marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Fix the NAND structures in bubt command according to latest
> changes in MTD API.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Igal Liberman <igall@marvell.com>
> Cc: Nadav Haklai <nadavh@marvell.com>

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

[U-Boot] [PATCH 1/5] fix: nand: pxa3xx: Remove hardcode values from the driver

[Stefan Roese]

On 28.03.2017 17:16, kostap at marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Obtain NAND controller setup parameters from the device
> tree instead of using hardcoded values.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> Cc: Scott Wood <oss@buserror.net>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Igal Liberman <igall@marvell.com>
> Cc: Nadav Haklai <nadavh@marvell.com>

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

[U-Boot] [PATCH 1/5] fix: nand: pxa3xx: Remove hardcode values from the driver

[Stefan Roese]

On 28.03.2017 17:16, kostap at marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Obtain NAND controller setup parameters from the device
> tree instead of using hardcoded values.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> Cc: Scott Wood <oss@buserror.net>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Igal Liberman <igall@marvell.com>
> Cc: Nadav Haklai <nadavh@marvell.com>

Applied to u-boot-marvell/master.

Thanks,
Stefan

[U-Boot] [PATCH 3/5] arm64: mvebu: Fix the bubt comamnd NAND device support

[Stefan Roese]

On 28.03.2017 17:16, kostap at marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Fix the NAND structures in bubt command according to latest
> changes in MTD API.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Igal Liberman <igall@marvell.com>
> Cc: Nadav Haklai <nadavh@marvell.com>

Applied to u-boot-marvell/master.

Thanks,
Stefan