From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bernard Iremonger Subject: [PATCH v4 1/5] net/i40e: initialise L3 MAP register Date: Wed, 29 Mar 2017 17:41:45 +0100 Message-ID: <1490805709-11997-2-git-send-email-bernard.iremonger@intel.com> References: <1490718059-380-1-git-send-email-bernard.iremonger@intel.com> Cc: helin.zhang@intel.com, wenzhuo.lu@intel.com, Bernard Iremonger To: dev@dpdk.org, beilei.xing@intel.com, jingjing.wu@intel.com Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 7514EF97A for ; Wed, 29 Mar 2017 18:41:59 +0200 (CEST) In-Reply-To: <1490718059-380-1-git-send-email-bernard.iremonger@intel.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The L3 MAP register is initialised to support QinQ cloud filters. Signed-off-by: Bernard Iremonger --- drivers/net/i40e/i40e_ethdev.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index e9f22e781..dafc995a1 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -686,6 +686,9 @@ RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio"); #ifndef I40E_GLQF_PIT #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) #endif +#ifndef I40E_GLQF_L3_MAP +#define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4)) +#endif static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) { @@ -1127,6 +1130,11 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) ((hw->nvm.version >> 4) & 0xff), (hw->nvm.version & 0xf), hw->nvm.eetrack); + /* initialise the L3_MAP register */ + ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40), 0x00000028, NULL); + if (ret) + PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret); + /* Need the special FW version to support floating VEB */ config_floating_veb(dev); /* Clear PXE mode */ -- 2.11.0