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From: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "Conselvan De Oliveira,
	Ander" <ander.conselvan.de.oliveira@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Zanoni, Paulo R" <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK
Date: Wed, 29 Mar 2017 21:16:36 +0000	[thread overview]
Message-ID: <1490823357.31644.39.camel@dk-H97M-D3H> (raw)
In-Reply-To: <20170329085006.GQ30290@intel.com>

On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote:
> On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote:
> > According to BSpec, "The CD clock frequency must be at least twice the
> > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> > default. This check is needed because BXT and GLK support cdclk
> > frequencies less than 192 MHz.
> > 
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index e8c1181..7b1ac1d 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> >  			pixel_rate = max(432000, pixel_rate);
> >  	}
> >  
> > +	/* According to BSpec, "The CD clock frequency must be at least twice
> > +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> > +	 * The check for GLK has to be adjusted as the platform can output
> > +	 * two pixels per clock.
> > +	 */
> > +	if (crtc_state->has_audio) {
> > +		if (IS_GEMINILAKE(dev_priv))
> > +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> 
> BTW that x2 factor for GLK looks wrong. It should be /2.
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=100439
> 

BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk
> 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a
factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk,
which are lower than 192 MHz.


	static int glk_calc_cdclk(int max_pixclk)
	{
	        if (max_pixclk > 2 * 158400)
        	        return 316800;
	        else if (max_pixclk > 2 * 79200)
        	        return 158400;
        	else
        	        return 79200;
	}

[1] Geminilake Clocks
"158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is
96 MHz)
316.8 MHz CD
79.2 MHz CD (exclusively for resolutions up to 1080p in low power single
pipe eDP/MIPI configurations, no audio support)"



-DK

> > +		if (IS_BROXTON(dev_priv))
> > +			pixel_rate = max(2 * 96000, pixel_rate);
> > +	}
> > +
> >  	return pixel_rate;
> >  }
> >  
> > -- 
> > 2.7.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2017-03-29 21:16 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-08  0:12 [PATCH v2 1/2] drm/i915/glk: Apply cdclk workaround for DP audio Dhinakaran Pandiyan
2017-03-08  0:12 ` [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK Dhinakaran Pandiyan
2017-03-14 20:47   ` Paulo Zanoni
2017-03-14 21:01     ` Pandiyan, Dhinakaran
2017-03-15  9:32       ` Jani Nikula
2017-03-15 18:03         ` Pandiyan, Dhinakaran
2017-03-15 18:16           ` Ville Syrjälä
2017-03-15 18:39             ` Paulo Zanoni
2017-03-15 19:30               ` Ville Syrjälä
2017-03-14 22:45     ` [PATCH v3 " Dhinakaran Pandiyan
2017-03-21 20:27       ` Paulo Zanoni
2017-03-29  8:50   ` [PATCH v2 " Ville Syrjälä
2017-03-29 21:16     ` Pandiyan, Dhinakaran [this message]
2017-03-30 11:42       ` Ville Syrjälä
2017-03-30 12:17         ` [Intel-gfx] " Takashi Iwai
2017-03-30 12:44           ` Ville Syrjälä
2017-03-30 18:14             ` Pandiyan, Dhinakaran
2017-03-08  0:48 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/glk: Apply cdclk workaround for DP audio Patchwork
2017-03-14 20:24 ` [PATCH v2 1/2] " Paulo Zanoni
2017-03-15  8:33 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/glk: Apply cdclk workaround for DP audio (rev2) Patchwork
2017-03-15  8:47 ` ✓ Fi.CI.BAT: success " Patchwork

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