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From: Alexey.Brodkin@synopsys.com (Alexey Brodkin)
To: linux-snps-arc@lists.infradead.org
Subject: [PATCH] arcv2: Make sure busy bit is set properly on SLC flushing
Date: Thu, 30 Mar 2017 14:26:30 +0000	[thread overview]
Message-ID: <1490883989.7449.3.camel@synopsys.com> (raw)
In-Reply-To: <35ad9cda-d493-869f-c65b-9d1ad5382ff3@synopsys.com>

Hi Vineet,

On Wed, 2017-03-29@16:41 -0700, Vineet Gupta wrote:
> On 03/29/2017 07:15 AM, Alexey Brodkin wrote:
> > 
> > As reported in STAR 9001165532 if data cache gets disabled right before
> > L2 cache invalidation we may read wrong value of L2 cache "busy" bit.
> > So we won't wait before L2 cache gets properly flushed and so some
> > data might not reach DDR at all thus we'll use older values from DDR
> > next time they are accessed.
> > 
> > For now we use a work-around with one extra read from SLC's control
> > register which guarantees next read will return real value of "busy"
> > bit.
> > 
> > Signed-off-by: Alexey Brodkin <abrodkin at synopsys.com>
> 
> Thx Alexey - pushed to for-curr !

Care to add for-stable tag?

-Alexey

      reply	other threads:[~2017-03-30 14:26 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1490796911-4848-1-git-send-email-abrodkin@synopsys.com>
2017-03-29 23:41 ` [PATCH] arcv2: Make sure busy bit is set properly on SLC flushing Vineet Gupta
2017-03-30 14:26   ` Alexey Brodkin [this message]

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