* [PATCH 1/8] drm/amdgpu: fix VMHUB order to match the hardware
@ 2017-04-03 12:39 Christian König
[not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
0 siblings, 1 reply; 13+ messages in thread
From: Christian König @ 2017-04-03 12:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Christian König <christian.koenig@amd.com>
Match our defines with what the hw uses.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++---------
2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 86fba1a..c156534 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -126,8 +126,8 @@ extern int amdgpu_param_buf_per_se;
/* max number of VMHUB */
#define AMDGPU_MAX_VMHUBS 2
-#define AMDGPU_MMHUB 0
-#define AMDGPU_GFXHUB 1
+#define AMDGPU_GFXHUB 0
+#define AMDGPU_MMHUB 1
/* hardcode that limit for now */
#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index df69aae..8dd99b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -129,8 +129,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
- struct amdgpu_vmhub *gfxhub = &adev->vmhub[AMDGPU_GFXHUB];
- struct amdgpu_vmhub *mmhub = &adev->vmhub[AMDGPU_MMHUB];
+ struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
uint32_t status = 0;
u64 addr;
@@ -138,13 +137,8 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
addr |= ((u64)entry->src_data[1] & 0xf) << 44;
if (!amdgpu_sriov_vf(adev)) {
- if (entry->vm_id_src) {
- status = RREG32(mmhub->vm_l2_pro_fault_status);
- WREG32_P(mmhub->vm_l2_pro_fault_cntl, 1, ~1);
- } else {
- status = RREG32(gfxhub->vm_l2_pro_fault_status);
- WREG32_P(gfxhub->vm_l2_pro_fault_cntl, 1, ~1);
- }
+ status = RREG32(hub->vm_l2_pro_fault_status);
+ WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
}
if (printk_ratelimit()) {
--
2.5.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/8] drm/amdgpu: move VM related defines into amdgpu_vm.h
[not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-04-03 12:39 ` Christian König
2017-04-03 12:39 ` [PATCH 3/8] drm/amdgpu: remove VMID first tracking Christian König
` (6 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Christian König @ 2017-04-03 12:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Christian König <christian.koenig@amd.com>
Try to clean up amdgpu.h.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 --------
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 8 ++++++++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c156534..8443e30 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -124,14 +124,6 @@ extern int amdgpu_param_buf_per_se;
/* max number of IP instances */
#define AMDGPU_MAX_SDMA_INSTANCES 2
-/* max number of VMHUB */
-#define AMDGPU_MAX_VMHUBS 2
-#define AMDGPU_GFXHUB 0
-#define AMDGPU_MMHUB 1
-
-/* hardcode that limit for now */
-#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
-
/* hard reset data */
#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 102b1f7..357cc56 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -76,6 +76,14 @@ struct amdgpu_bo_list_entry;
#define AMDGPU_VM_FAULT_STOP_FIRST 1
#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
+/* max number of VMHUB */
+#define AMDGPU_MAX_VMHUBS 2
+#define AMDGPU_GFXHUB 0
+#define AMDGPU_MMHUB 1
+
+/* hardcode that limit for now */
+#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
+
struct amdgpu_vm_pt {
struct amdgpu_bo *bo;
uint64_t addr;
--
2.5.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/8] drm/amdgpu: remove VMID first tracking
[not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-03 12:39 ` [PATCH 2/8] drm/amdgpu: move VM related defines into amdgpu_vm.h Christian König
@ 2017-04-03 12:39 ` Christian König
2017-04-03 12:39 ` [PATCH 4/8] drm/amdgpu: coding style of amdgpu_vm_is_gpu_reset Christian König
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Christian König @ 2017-04-03 12:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Christian König <christian.koenig@amd.com>
Not used any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ----
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 -
2 files changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 43adc4b..713e251 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -514,9 +514,6 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
if (r)
goto error;
- fence_put(id->first);
- id->first = fence_get(fence);
-
fence_put(id->last_flush);
id->last_flush = NULL;
@@ -2231,7 +2228,6 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
for (i = 0; i < AMDGPU_NUM_VM; ++i) {
struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
- fence_put(adev->vm_manager.ids[i].first);
amdgpu_sync_free(&adev->vm_manager.ids[i].active);
fence_put(id->flushed_updates);
fence_put(id->last_flush);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 357cc56..1b0918a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -131,7 +131,6 @@ struct amdgpu_vm {
struct amdgpu_vm_id {
struct list_head list;
- struct fence *first;
struct amdgpu_sync active;
struct fence *last_flush;
atomic64_t owner;
--
2.5.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/8] drm/amdgpu: coding style of amdgpu_vm_is_gpu_reset
[not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-03 12:39 ` [PATCH 2/8] drm/amdgpu: move VM related defines into amdgpu_vm.h Christian König
2017-04-03 12:39 ` [PATCH 3/8] drm/amdgpu: remove VMID first tracking Christian König
@ 2017-04-03 12:39 ` Christian König
2017-04-03 12:39 ` [PATCH 5/8] drm/amdgpu: cleanup coding style in amdgpu_vm_flush Christian König
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Christian König @ 2017-04-03 12:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Christian König <christian.koenig@amd.com>
The name is a bit confusing and the extra "? true : false" is superflous.
Additional to that remove setting the reset counter directly after checking it.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 713e251..4ffd2244 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -375,11 +375,19 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0);
}
-static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev,
- struct amdgpu_vm_id *id)
+/**
+ * amdgpu_vm_had_gpu_reset - check if reset occured since last use
+ *
+ * @adev: amdgpu_device pointer
+ * @id: VMID structure
+ *
+ * Check if GPU reset occured since last use of the VMID.
+ */
+static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev,
+ struct amdgpu_vm_id *id)
{
return id->current_gpu_reset_count !=
- atomic_read(&adev->gpu_reset_counter) ? true : false;
+ atomic_read(&adev->gpu_reset_counter);
}
/**
@@ -465,7 +473,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
/* Check all the prerequisites to using this VMID */
if (!id)
continue;
- if (amdgpu_vm_is_gpu_reset(adev, id))
+ if (amdgpu_vm_had_gpu_reset(adev, id))
continue;
if (atomic64_read(&id->owner) != vm->client_id)
@@ -493,7 +501,6 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
if (r)
goto error;
- id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
list_move_tail(&id->list, &adev->vm_manager.ids_lru);
vm->ids[ring->idx] = id;
@@ -593,7 +600,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
int r;
if (job->vm_needs_flush || gds_switch_needed ||
- amdgpu_vm_is_gpu_reset(adev, id) ||
+ amdgpu_vm_had_gpu_reset(adev, id) ||
amdgpu_vm_ring_has_compute_vm_bug(ring)) {
unsigned patch_offset = 0;
@@ -606,7 +613,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
amdgpu_ring_emit_pipeline_sync(ring);
if (ring->funcs->emit_vm_flush && (job->vm_needs_flush ||
- amdgpu_vm_is_gpu_reset(adev, id))) {
+ amdgpu_vm_had_gpu_reset(adev, id))) {
struct fence *fence;
u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
--
2.5.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/8] drm/amdgpu: cleanup coding style in amdgpu_vm_flush
[not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
` (2 preceding siblings ...)
2017-04-03 12:39 ` [PATCH 4/8] drm/amdgpu: coding style of amdgpu_vm_is_gpu_reset Christian König
@ 2017-04-03 12:39 ` Christian König
[not found] ` <1491223199-28892-5-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-03 12:39 ` [PATCH 6/8] drm/amdgpu: cleanup logic " Christian König
` (3 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Christian König @ 2017-04-03 12:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Christian König <christian.koenig@amd.com>
The indentation was of in more than one place.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 88 +++++++++++++++++-----------------
1 file changed, 45 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 4ffd2244..85e45b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -597,60 +597,62 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
id->gws_size != job->gws_size ||
id->oa_base != job->oa_base ||
id->oa_size != job->oa_size);
+ unsigned patch_offset = 0;
int r;
- if (job->vm_needs_flush || gds_switch_needed ||
- amdgpu_vm_had_gpu_reset(adev, id) ||
- amdgpu_vm_ring_has_compute_vm_bug(ring)) {
- unsigned patch_offset = 0;
+ if (!job->vm_needs_flush && !gds_switch_needed &&
+ !amdgpu_vm_had_gpu_reset(adev, id) &&
+ !amdgpu_vm_ring_has_compute_vm_bug(ring))
+ return 0;
- if (ring->funcs->init_cond_exec)
- patch_offset = amdgpu_ring_init_cond_exec(ring);
- if (ring->funcs->emit_pipeline_sync &&
- (job->vm_needs_flush || gds_switch_needed ||
- amdgpu_vm_ring_has_compute_vm_bug(ring)))
- amdgpu_ring_emit_pipeline_sync(ring);
+ if (ring->funcs->init_cond_exec)
+ patch_offset = amdgpu_ring_init_cond_exec(ring);
- if (ring->funcs->emit_vm_flush && (job->vm_needs_flush ||
- amdgpu_vm_had_gpu_reset(adev, id))) {
- struct fence *fence;
- u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
+ if (ring->funcs->emit_pipeline_sync &&
+ (job->vm_needs_flush || gds_switch_needed ||
+ amdgpu_vm_ring_has_compute_vm_bug(ring)))
+ amdgpu_ring_emit_pipeline_sync(ring);
- trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
- amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
+ if (ring->funcs->emit_vm_flush &&
+ (job->vm_needs_flush || amdgpu_vm_had_gpu_reset(adev, id))) {
- r = amdgpu_fence_emit(ring, &fence);
- if (r)
- return r;
+ u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
+ struct fence *fence;
- mutex_lock(&adev->vm_manager.lock);
- fence_put(id->last_flush);
- id->last_flush = fence;
- mutex_unlock(&adev->vm_manager.lock);
- }
+ trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
+ amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
- if (gds_switch_needed) {
- id->gds_base = job->gds_base;
- id->gds_size = job->gds_size;
- id->gws_base = job->gws_base;
- id->gws_size = job->gws_size;
- id->oa_base = job->oa_base;
- id->oa_size = job->oa_size;
- amdgpu_ring_emit_gds_switch(ring, job->vm_id,
- job->gds_base, job->gds_size,
- job->gws_base, job->gws_size,
- job->oa_base, job->oa_size);
- }
+ r = amdgpu_fence_emit(ring, &fence);
+ if (r)
+ return r;
- if (ring->funcs->patch_cond_exec)
- amdgpu_ring_patch_cond_exec(ring, patch_offset);
+ mutex_lock(&adev->vm_manager.lock);
+ fence_put(id->last_flush);
+ id->last_flush = fence;
+ mutex_unlock(&adev->vm_manager.lock);
+ }
- /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
- if (ring->funcs->emit_switch_buffer) {
- amdgpu_ring_emit_switch_buffer(ring);
- amdgpu_ring_emit_switch_buffer(ring);
- }
+ if (gds_switch_needed) {
+ id->gds_base = job->gds_base;
+ id->gds_size = job->gds_size;
+ id->gws_base = job->gws_base;
+ id->gws_size = job->gws_size;
+ id->oa_base = job->oa_base;
+ id->oa_size = job->oa_size;
+ amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base,
+ job->gds_size, job->gws_base,
+ job->gws_size, job->oa_base,
+ job->oa_size);
+ }
+
+ if (ring->funcs->patch_cond_exec)
+ amdgpu_ring_patch_cond_exec(ring, patch_offset);
+
+ /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
+ if (ring->funcs->emit_switch_buffer) {
+ amdgpu_ring_emit_switch_buffer(ring);
+ amdgpu_ring_emit_switch_buffer(ring);
}
return 0;
}
--
2.5.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 6/8] drm/amdgpu: cleanup logic in amdgpu_vm_flush
[not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
` (3 preceding siblings ...)
2017-04-03 12:39 ` [PATCH 5/8] drm/amdgpu: cleanup coding style in amdgpu_vm_flush Christian König
@ 2017-04-03 12:39 ` Christian König
2017-04-03 12:39 ` [PATCH 7/8] drm/amdgpu: move adjust_mc_addr into amdgpu_gart_funcs Christian König
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Christian König @ 2017-04-03 12:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Christian König <christian.koenig@amd.com>
Remove some of the extra checks where they don't hurt us.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 85e45b3..cbb5b25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -597,26 +597,26 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
id->gws_size != job->gws_size ||
id->oa_base != job->oa_base ||
id->oa_size != job->oa_size);
+ bool vm_flush_needed = job->vm_needs_flush ||
+ amdgpu_vm_ring_has_compute_vm_bug(ring);
unsigned patch_offset = 0;
int r;
- if (!job->vm_needs_flush && !gds_switch_needed &&
- !amdgpu_vm_had_gpu_reset(adev, id) &&
- !amdgpu_vm_ring_has_compute_vm_bug(ring))
- return 0;
+ if (amdgpu_vm_had_gpu_reset(adev, id)) {
+ gds_switch_needed = true;
+ vm_flush_needed = true;
+ }
+ if (!vm_flush_needed && !gds_switch_needed)
+ return 0;
if (ring->funcs->init_cond_exec)
patch_offset = amdgpu_ring_init_cond_exec(ring);
- if (ring->funcs->emit_pipeline_sync &&
- (job->vm_needs_flush || gds_switch_needed ||
- amdgpu_vm_ring_has_compute_vm_bug(ring)))
+ if (ring->funcs->emit_pipeline_sync)
amdgpu_ring_emit_pipeline_sync(ring);
- if (ring->funcs->emit_vm_flush &&
- (job->vm_needs_flush || amdgpu_vm_had_gpu_reset(adev, id))) {
-
+ if (ring->funcs->emit_vm_flush && vm_flush_needed) {
u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
struct fence *fence;
--
2.5.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 7/8] drm/amdgpu: move adjust_mc_addr into amdgpu_gart_funcs
[not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
` (4 preceding siblings ...)
2017-04-03 12:39 ` [PATCH 6/8] drm/amdgpu: cleanup logic " Christian König
@ 2017-04-03 12:39 ` Christian König
2017-04-03 12:39 ` [PATCH 8/8] drm/amdgpu: cleanup VMHUB bit definitions Christian König
2017-04-03 19:23 ` [PATCH 1/8] drm/amdgpu: fix VMHUB order to match the hardware Alex Deucher
7 siblings, 0 replies; 13+ messages in thread
From: Christian König @ 2017-04-03 12:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Christian König <christian.koenig@amd.com>
We should probably rename amdgpu_gart_funcs sooner or later.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 -----
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 23 +++++++----------------
3 files changed, 9 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8443e30..cc43fee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -306,10 +306,6 @@ struct amdgpu_gart_funcs {
/* set pte flags based per asic */
uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
uint32_t flags);
-};
-
-/* provided by the mc block */
-struct amdgpu_mc_funcs {
/* adjust mc addr in fb for APU case */
u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
};
@@ -615,7 +611,6 @@ struct amdgpu_mc {
u64 private_aperture_end;
/* protects concurrent invalidation */
spinlock_t invalidate_lock;
- const struct amdgpu_mc_funcs *mc_funcs;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index cbb5b25..fc5ee11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -571,8 +571,8 @@ static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
{
u64 addr = mc_addr;
- if (adev->mc.mc_funcs && adev->mc.mc_funcs->adjust_mc_addr)
- addr = adev->mc.mc_funcs->adjust_mc_addr(adev, addr);
+ if (adev->gart.gart_funcs->adjust_mc_addr)
+ addr = adev->gart.gart_funcs->adjust_mc_addr(adev, addr);
return addr;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 8dd99b2..268cedb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -331,30 +331,22 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
return pte_flag;
}
-static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
- .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
- .set_pte_pde = gmc_v9_0_gart_set_pte_pde,
- .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags
-};
-
-static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
-{
- if (adev->gart.gart_funcs == NULL)
- adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
-}
-
static u64 gmc_v9_0_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
{
return adev->vm_manager.vram_base_offset + mc_addr - adev->mc.vram_start;
}
-static const struct amdgpu_mc_funcs gmc_v9_0_mc_funcs = {
+static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
+ .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
+ .set_pte_pde = gmc_v9_0_gart_set_pte_pde,
+ .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
.adjust_mc_addr = gmc_v9_0_adjust_mc_addr,
};
-static void gmc_v9_0_set_mc_funcs(struct amdgpu_device *adev)
+static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
{
- adev->mc.mc_funcs = &gmc_v9_0_mc_funcs;
+ if (adev->gart.gart_funcs == NULL)
+ adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
}
static int gmc_v9_0_early_init(void *handle)
@@ -362,7 +354,6 @@ static int gmc_v9_0_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gmc_v9_0_set_gart_funcs(adev);
- gmc_v9_0_set_mc_funcs(adev);
gmc_v9_0_set_irq_funcs(adev);
return 0;
--
2.5.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 8/8] drm/amdgpu: cleanup VMHUB bit definitions
[not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
` (5 preceding siblings ...)
2017-04-03 12:39 ` [PATCH 7/8] drm/amdgpu: move adjust_mc_addr into amdgpu_gart_funcs Christian König
@ 2017-04-03 12:39 ` Christian König
[not found] ` <1491223199-28892-8-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-03 19:23 ` [PATCH 1/8] drm/amdgpu: fix VMHUB order to match the hardware Alex Deucher
7 siblings, 1 reply; 13+ messages in thread
From: Christian König @ 2017-04-03 12:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Christian König <christian.koenig@amd.com>
The two hubs are just instances of the same hardware,
so the register bits are identical.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 --------------------------------
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 33 +++++++++++++++++++++++++++-----
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 2 ++
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33 --------------------------------
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 ++-
9 files changed, 39 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index cc43fee..f6f6dcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -572,8 +572,6 @@ struct amdgpu_vmhub {
uint32_t vm_context0_cntl;
uint32_t vm_l2_pro_fault_status;
uint32_t vm_l2_pro_fault_cntl;
- uint32_t (*get_invalidate_req)(unsigned int vm_id);
- uint32_t (*get_vm_protection_bits)(void);
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8a1c4e..4ae5ac0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -36,6 +36,7 @@
#include "soc15_common.h"
#include "clearstate_gfx9.h"
#include "v9_structs.h"
+#include "gmc_v9_0.h"
#define GFX9_NUM_GFX_RINGS 1
#define GFX9_NUM_COMPUTE_RINGS 8
@@ -3148,6 +3149,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
unsigned vm_id, uint64_t pd_addr)
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+ uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
unsigned eng = ring->idx;
unsigned i;
@@ -3157,7 +3159,6 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
- uint32_t req = hub->get_invalidate_req(vm_id);
gfx_v9_0_write_data_to_reg(ring, usepfp, true,
hub->ctx0_ptb_addr_lo32
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index dd48637..0abb128 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -299,36 +299,6 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
}
-static uint32_t gfxhub_v1_0_get_invalidate_req(unsigned int vm_id)
-{
- u32 req = 0;
-
- /* invalidate using legacy mode on vm_id*/
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
- PER_VMID_INVALIDATE_REQ, 1 << vm_id);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
- CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
-
- return req;
-}
-
-static uint32_t gfxhub_v1_0_get_vm_protection_bits(void)
-{
- return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
-}
-
static int gfxhub_v1_0_early_init(void *handle)
{
return 0;
@@ -361,9 +331,6 @@ static int gfxhub_v1_0_sw_init(void *handle)
hub->vm_l2_pro_fault_cntl =
SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
- hub->get_invalidate_req = gfxhub_v1_0_get_invalidate_req;
- hub->get_vm_protection_bits = gfxhub_v1_0_get_vm_protection_bits;
-
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 268cedb..43b429e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -75,11 +75,18 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_vmhub *hub;
u32 tmp, reg, bits, i;
+ bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
+
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
/* MM HUB */
hub = &adev->vmhub[AMDGPU_MMHUB];
- bits = hub->get_vm_protection_bits();
for (i = 0; i< 16; i++) {
reg = hub->vm_context0_cntl + i;
tmp = RREG32(reg);
@@ -89,7 +96,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
/* GFX HUB */
hub = &adev->vmhub[AMDGPU_GFXHUB];
- bits = hub->get_vm_protection_bits();
for (i = 0; i < 16; i++) {
reg = hub->vm_context0_cntl + i;
tmp = RREG32(reg);
@@ -100,7 +106,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
case AMDGPU_IRQ_STATE_ENABLE:
/* MM HUB */
hub = &adev->vmhub[AMDGPU_MMHUB];
- bits = hub->get_vm_protection_bits();
for (i = 0; i< 16; i++) {
reg = hub->vm_context0_cntl + i;
tmp = RREG32(reg);
@@ -110,7 +115,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
/* GFX HUB */
hub = &adev->vmhub[AMDGPU_GFXHUB];
- bits = hub->get_vm_protection_bits();
for (i = 0; i < 16; i++) {
reg = hub->vm_context0_cntl + i;
tmp = RREG32(reg);
@@ -169,6 +173,25 @@ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
}
+uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
+{
+ u32 req = 0;
+
+ /* invalidate using legacy mode on vm_id*/
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ PER_VMID_INVALIDATE_REQ, 1 << vm_id);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
+ CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
+
+ return req;
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -198,7 +221,7 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
struct amdgpu_vmhub *hub = &adev->vmhub[i];
- u32 tmp = hub->get_invalidate_req(vmid);
+ u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
index b030ca5..ea046a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
@@ -27,4 +27,6 @@
extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
+uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id);
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index c1dc8c4..6cd1c55 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -317,36 +317,6 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
}
-static uint32_t mmhub_v1_0_get_invalidate_req(unsigned int vm_id)
-{
- u32 req = 0;
-
- /* invalidate using legacy mode on vm_id*/
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
- PER_VMID_INVALIDATE_REQ, 1 << vm_id);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
- CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
-
- return req;
-}
-
-static uint32_t mmhub_v1_0_get_vm_protection_bits(void)
-{
- return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
-}
-
static int mmhub_v1_0_early_init(void *handle)
{
return 0;
@@ -379,9 +349,6 @@ static int mmhub_v1_0_sw_init(void *handle)
hub->vm_l2_pro_fault_cntl =
SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
- hub->get_invalidate_req = mmhub_v1_0_get_invalidate_req;
- hub->get_vm_protection_bits = mmhub_v1_0_get_vm_protection_bits;
-
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 6cfb100..e30ea26 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -39,6 +39,7 @@
#include "soc15_common.h"
#include "soc15.h"
#include "vega10_sdma_pkt_open.h"
+#include "gmc_v9_0.h"
MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
@@ -1039,6 +1040,7 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
unsigned vm_id, uint64_t pd_addr)
{
+ uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
unsigned eng = ring->idx;
unsigned i;
@@ -1048,7 +1050,6 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
- uint32_t req = hub->get_invalidate_req(vm_id);
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 3457546..593b04b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -27,6 +27,7 @@
#include "amdgpu_uvd.h"
#include "soc15d.h"
#include "soc15_common.h"
+#include "gmc_v9_0.h"
#include "vega10/soc15ip.h"
#include "vega10/UVD/uvd_7_0_offset.h"
@@ -1045,6 +1046,7 @@ static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
unsigned vm_id, uint64_t pd_addr)
{
+ uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
uint32_t data0, data1, mask;
unsigned eng = ring->idx;
unsigned i;
@@ -1055,7 +1057,6 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
- uint32_t req = hub->get_invalidate_req(vm_id);
data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
data1 = upper_32_bits(pd_addr);
@@ -1091,6 +1092,7 @@ static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
unsigned int vm_id, uint64_t pd_addr)
{
+ uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
unsigned eng = ring->idx;
unsigned i;
@@ -1100,7 +1102,6 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
- uint32_t req = hub->get_invalidate_req(vm_id);
amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
amdgpu_ring_write(ring,
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index ad5fd98..9c5ce91 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -31,6 +31,7 @@
#include "soc15d.h"
#include "soc15_common.h"
#include "mmsch_v1_0.h"
+#include "gmc_v9_0.h"
#include "vega10/soc15ip.h"
#include "vega10/VCE/vce_4_0_offset.h"
@@ -985,6 +986,7 @@ static void vce_v4_0_ring_insert_end(struct amdgpu_ring *ring)
static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
unsigned int vm_id, uint64_t pd_addr)
{
+ uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
unsigned eng = ring->idx;
unsigned i;
@@ -994,7 +996,6 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
- uint32_t req = hub->get_invalidate_req(vm_id);
amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
amdgpu_ring_write(ring,
--
2.5.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 5/8] drm/amdgpu: cleanup coding style in amdgpu_vm_flush
[not found] ` <1491223199-28892-5-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-04-03 19:18 ` Alex Deucher
0 siblings, 0 replies; 13+ messages in thread
From: Alex Deucher @ 2017-04-03 19:18 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx list
On Mon, Apr 3, 2017 at 8:39 AM, Christian König <deathsimple@vodafone.de> wrote:
> From: Christian König <christian.koenig@amd.com>
>
> The indentation was of in more than one place.
commit message is unclear, with that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 88 +++++++++++++++++-----------------
> 1 file changed, 45 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 4ffd2244..85e45b3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -597,60 +597,62 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
> id->gws_size != job->gws_size ||
> id->oa_base != job->oa_base ||
> id->oa_size != job->oa_size);
> + unsigned patch_offset = 0;
> int r;
>
> - if (job->vm_needs_flush || gds_switch_needed ||
> - amdgpu_vm_had_gpu_reset(adev, id) ||
> - amdgpu_vm_ring_has_compute_vm_bug(ring)) {
> - unsigned patch_offset = 0;
> + if (!job->vm_needs_flush && !gds_switch_needed &&
> + !amdgpu_vm_had_gpu_reset(adev, id) &&
> + !amdgpu_vm_ring_has_compute_vm_bug(ring))
> + return 0;
>
> - if (ring->funcs->init_cond_exec)
> - patch_offset = amdgpu_ring_init_cond_exec(ring);
>
> - if (ring->funcs->emit_pipeline_sync &&
> - (job->vm_needs_flush || gds_switch_needed ||
> - amdgpu_vm_ring_has_compute_vm_bug(ring)))
> - amdgpu_ring_emit_pipeline_sync(ring);
> + if (ring->funcs->init_cond_exec)
> + patch_offset = amdgpu_ring_init_cond_exec(ring);
>
> - if (ring->funcs->emit_vm_flush && (job->vm_needs_flush ||
> - amdgpu_vm_had_gpu_reset(adev, id))) {
> - struct fence *fence;
> - u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
> + if (ring->funcs->emit_pipeline_sync &&
> + (job->vm_needs_flush || gds_switch_needed ||
> + amdgpu_vm_ring_has_compute_vm_bug(ring)))
> + amdgpu_ring_emit_pipeline_sync(ring);
>
> - trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
> - amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
> + if (ring->funcs->emit_vm_flush &&
> + (job->vm_needs_flush || amdgpu_vm_had_gpu_reset(adev, id))) {
>
> - r = amdgpu_fence_emit(ring, &fence);
> - if (r)
> - return r;
> + u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
> + struct fence *fence;
>
> - mutex_lock(&adev->vm_manager.lock);
> - fence_put(id->last_flush);
> - id->last_flush = fence;
> - mutex_unlock(&adev->vm_manager.lock);
> - }
> + trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
> + amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
>
> - if (gds_switch_needed) {
> - id->gds_base = job->gds_base;
> - id->gds_size = job->gds_size;
> - id->gws_base = job->gws_base;
> - id->gws_size = job->gws_size;
> - id->oa_base = job->oa_base;
> - id->oa_size = job->oa_size;
> - amdgpu_ring_emit_gds_switch(ring, job->vm_id,
> - job->gds_base, job->gds_size,
> - job->gws_base, job->gws_size,
> - job->oa_base, job->oa_size);
> - }
> + r = amdgpu_fence_emit(ring, &fence);
> + if (r)
> + return r;
>
> - if (ring->funcs->patch_cond_exec)
> - amdgpu_ring_patch_cond_exec(ring, patch_offset);
> + mutex_lock(&adev->vm_manager.lock);
> + fence_put(id->last_flush);
> + id->last_flush = fence;
> + mutex_unlock(&adev->vm_manager.lock);
> + }
>
> - /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
> - if (ring->funcs->emit_switch_buffer) {
> - amdgpu_ring_emit_switch_buffer(ring);
> - amdgpu_ring_emit_switch_buffer(ring);
> - }
> + if (gds_switch_needed) {
> + id->gds_base = job->gds_base;
> + id->gds_size = job->gds_size;
> + id->gws_base = job->gws_base;
> + id->gws_size = job->gws_size;
> + id->oa_base = job->oa_base;
> + id->oa_size = job->oa_size;
> + amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base,
> + job->gds_size, job->gws_base,
> + job->gws_size, job->oa_base,
> + job->oa_size);
> + }
> +
> + if (ring->funcs->patch_cond_exec)
> + amdgpu_ring_patch_cond_exec(ring, patch_offset);
> +
> + /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
> + if (ring->funcs->emit_switch_buffer) {
> + amdgpu_ring_emit_switch_buffer(ring);
> + amdgpu_ring_emit_switch_buffer(ring);
> }
> return 0;
> }
> --
> 2.5.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/8] drm/amdgpu: fix VMHUB order to match the hardware
[not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
` (6 preceding siblings ...)
2017-04-03 12:39 ` [PATCH 8/8] drm/amdgpu: cleanup VMHUB bit definitions Christian König
@ 2017-04-03 19:23 ` Alex Deucher
[not found] ` <CADnq5_NHtW=w2YfZw4=3G-rsYRyxyGJ0NPRormJtB6p+BqUjfg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
7 siblings, 1 reply; 13+ messages in thread
From: Alex Deucher @ 2017-04-03 19:23 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx list
On Mon, Apr 3, 2017 at 8:39 AM, Christian König <deathsimple@vodafone.de> wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Match our defines with what the hw uses.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Patches 1-4, 6-7:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++---------
> 2 files changed, 5 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 86fba1a..c156534 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -126,8 +126,8 @@ extern int amdgpu_param_buf_per_se;
>
> /* max number of VMHUB */
> #define AMDGPU_MAX_VMHUBS 2
> -#define AMDGPU_MMHUB 0
> -#define AMDGPU_GFXHUB 1
> +#define AMDGPU_GFXHUB 0
> +#define AMDGPU_MMHUB 1
>
> /* hardcode that limit for now */
> #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index df69aae..8dd99b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -129,8 +129,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
> struct amdgpu_irq_src *source,
> struct amdgpu_iv_entry *entry)
> {
> - struct amdgpu_vmhub *gfxhub = &adev->vmhub[AMDGPU_GFXHUB];
> - struct amdgpu_vmhub *mmhub = &adev->vmhub[AMDGPU_MMHUB];
> + struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
> uint32_t status = 0;
> u64 addr;
>
> @@ -138,13 +137,8 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
> addr |= ((u64)entry->src_data[1] & 0xf) << 44;
>
> if (!amdgpu_sriov_vf(adev)) {
> - if (entry->vm_id_src) {
> - status = RREG32(mmhub->vm_l2_pro_fault_status);
> - WREG32_P(mmhub->vm_l2_pro_fault_cntl, 1, ~1);
> - } else {
> - status = RREG32(gfxhub->vm_l2_pro_fault_status);
> - WREG32_P(gfxhub->vm_l2_pro_fault_cntl, 1, ~1);
> - }
> + status = RREG32(hub->vm_l2_pro_fault_status);
> + WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
> }
>
> if (printk_ratelimit()) {
> --
> 2.5.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 8/8] drm/amdgpu: cleanup VMHUB bit definitions
[not found] ` <1491223199-28892-8-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-04-03 19:31 ` Alex Deucher
[not found] ` <CADnq5_M+jYQU6Utw8OrLeFurwsnw=5Y1EdgwXGnhBDrqtszhcQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 13+ messages in thread
From: Alex Deucher @ 2017-04-03 19:31 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx list
On Mon, Apr 3, 2017 at 8:39 AM, Christian König <deathsimple@vodafone.de> wrote:
> From: Christian König <christian.koenig@amd.com>
>
> The two hubs are just instances of the same hardware,
> so the register bits are identical.
Removing get_vm_protection_bits makes sense since those are limited to
the gmc module. I'd prefer to keep get_invalidation_req since that
protects the ip modules from a direct dependency on gmc9. We'd end up
reimplementing this when we come to an ip module that ends up being
used on a chip with a newer gmc. Also seems cleaner this way in my
opinion.
Alex
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 --------------------------------
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 33 +++++++++++++++++++++++++++-----
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 2 ++
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33 --------------------------------
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 5 +++--
> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 ++-
> 9 files changed, 39 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index cc43fee..f6f6dcb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -572,8 +572,6 @@ struct amdgpu_vmhub {
> uint32_t vm_context0_cntl;
> uint32_t vm_l2_pro_fault_status;
> uint32_t vm_l2_pro_fault_cntl;
> - uint32_t (*get_invalidate_req)(unsigned int vm_id);
> - uint32_t (*get_vm_protection_bits)(void);
> };
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index c8a1c4e..4ae5ac0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -36,6 +36,7 @@
> #include "soc15_common.h"
> #include "clearstate_gfx9.h"
> #include "v9_structs.h"
> +#include "gmc_v9_0.h"
>
> #define GFX9_NUM_GFX_RINGS 1
> #define GFX9_NUM_COMPUTE_RINGS 8
> @@ -3148,6 +3149,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
> unsigned vm_id, uint64_t pd_addr)
> {
> int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
> unsigned eng = ring->idx;
> unsigned i;
>
> @@ -3157,7 +3159,6 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>
> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
> - uint32_t req = hub->get_invalidate_req(vm_id);
>
> gfx_v9_0_write_data_to_reg(ring, usepfp, true,
> hub->ctx0_ptb_addr_lo32
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index dd48637..0abb128 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -299,36 +299,6 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
> WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
> }
>
> -static uint32_t gfxhub_v1_0_get_invalidate_req(unsigned int vm_id)
> -{
> - u32 req = 0;
> -
> - /* invalidate using legacy mode on vm_id*/
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
> - PER_VMID_INVALIDATE_REQ, 1 << vm_id);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
> - CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
> -
> - return req;
> -}
> -
> -static uint32_t gfxhub_v1_0_get_vm_protection_bits(void)
> -{
> - return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
> -}
> -
> static int gfxhub_v1_0_early_init(void *handle)
> {
> return 0;
> @@ -361,9 +331,6 @@ static int gfxhub_v1_0_sw_init(void *handle)
> hub->vm_l2_pro_fault_cntl =
> SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
>
> - hub->get_invalidate_req = gfxhub_v1_0_get_invalidate_req;
> - hub->get_vm_protection_bits = gfxhub_v1_0_get_vm_protection_bits;
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 268cedb..43b429e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -75,11 +75,18 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
> struct amdgpu_vmhub *hub;
> u32 tmp, reg, bits, i;
>
> + bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> + VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
> +
> switch (state) {
> case AMDGPU_IRQ_STATE_DISABLE:
> /* MM HUB */
> hub = &adev->vmhub[AMDGPU_MMHUB];
> - bits = hub->get_vm_protection_bits();
> for (i = 0; i< 16; i++) {
> reg = hub->vm_context0_cntl + i;
> tmp = RREG32(reg);
> @@ -89,7 +96,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>
> /* GFX HUB */
> hub = &adev->vmhub[AMDGPU_GFXHUB];
> - bits = hub->get_vm_protection_bits();
> for (i = 0; i < 16; i++) {
> reg = hub->vm_context0_cntl + i;
> tmp = RREG32(reg);
> @@ -100,7 +106,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
> case AMDGPU_IRQ_STATE_ENABLE:
> /* MM HUB */
> hub = &adev->vmhub[AMDGPU_MMHUB];
> - bits = hub->get_vm_protection_bits();
> for (i = 0; i< 16; i++) {
> reg = hub->vm_context0_cntl + i;
> tmp = RREG32(reg);
> @@ -110,7 +115,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>
> /* GFX HUB */
> hub = &adev->vmhub[AMDGPU_GFXHUB];
> - bits = hub->get_vm_protection_bits();
> for (i = 0; i < 16; i++) {
> reg = hub->vm_context0_cntl + i;
> tmp = RREG32(reg);
> @@ -169,6 +173,25 @@ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
> adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
> }
>
> +uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
> +{
> + u32 req = 0;
> +
> + /* invalidate using legacy mode on vm_id*/
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
> + PER_VMID_INVALIDATE_REQ, 1 << vm_id);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
> + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
> +
> + return req;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -198,7 +221,7 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
>
> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
> struct amdgpu_vmhub *hub = &adev->vmhub[i];
> - u32 tmp = hub->get_invalidate_req(vmid);
> + u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
>
> WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
> index b030ca5..ea046a8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
> @@ -27,4 +27,6 @@
> extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
> extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
>
> +uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id);
> +
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index c1dc8c4..6cd1c55 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -317,36 +317,6 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
> WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
> }
>
> -static uint32_t mmhub_v1_0_get_invalidate_req(unsigned int vm_id)
> -{
> - u32 req = 0;
> -
> - /* invalidate using legacy mode on vm_id*/
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
> - PER_VMID_INVALIDATE_REQ, 1 << vm_id);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
> - CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
> -
> - return req;
> -}
> -
> -static uint32_t mmhub_v1_0_get_vm_protection_bits(void)
> -{
> - return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> - VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
> -}
> -
> static int mmhub_v1_0_early_init(void *handle)
> {
> return 0;
> @@ -379,9 +349,6 @@ static int mmhub_v1_0_sw_init(void *handle)
> hub->vm_l2_pro_fault_cntl =
> SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
>
> - hub->get_invalidate_req = mmhub_v1_0_get_invalidate_req;
> - hub->get_vm_protection_bits = mmhub_v1_0_get_vm_protection_bits;
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 6cfb100..e30ea26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -39,6 +39,7 @@
> #include "soc15_common.h"
> #include "soc15.h"
> #include "vega10_sdma_pkt_open.h"
> +#include "gmc_v9_0.h"
>
> MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
> MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
> @@ -1039,6 +1040,7 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
> static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
> unsigned vm_id, uint64_t pd_addr)
> {
> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
> unsigned eng = ring->idx;
> unsigned i;
>
> @@ -1048,7 +1050,6 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>
> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
> - uint32_t req = hub->get_invalidate_req(vm_id);
>
> amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
> SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 3457546..593b04b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -27,6 +27,7 @@
> #include "amdgpu_uvd.h"
> #include "soc15d.h"
> #include "soc15_common.h"
> +#include "gmc_v9_0.h"
>
> #include "vega10/soc15ip.h"
> #include "vega10/UVD/uvd_7_0_offset.h"
> @@ -1045,6 +1046,7 @@ static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
> static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
> unsigned vm_id, uint64_t pd_addr)
> {
> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
> uint32_t data0, data1, mask;
> unsigned eng = ring->idx;
> unsigned i;
> @@ -1055,7 +1057,6 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>
> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
> - uint32_t req = hub->get_invalidate_req(vm_id);
>
> data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
> data1 = upper_32_bits(pd_addr);
> @@ -1091,6 +1092,7 @@ static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
> static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
> unsigned int vm_id, uint64_t pd_addr)
> {
> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
> unsigned eng = ring->idx;
> unsigned i;
>
> @@ -1100,7 +1102,6 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>
> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
> - uint32_t req = hub->get_invalidate_req(vm_id);
>
> amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
> amdgpu_ring_write(ring,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index ad5fd98..9c5ce91 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -31,6 +31,7 @@
> #include "soc15d.h"
> #include "soc15_common.h"
> #include "mmsch_v1_0.h"
> +#include "gmc_v9_0.h"
>
> #include "vega10/soc15ip.h"
> #include "vega10/VCE/vce_4_0_offset.h"
> @@ -985,6 +986,7 @@ static void vce_v4_0_ring_insert_end(struct amdgpu_ring *ring)
> static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
> unsigned int vm_id, uint64_t pd_addr)
> {
> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
> unsigned eng = ring->idx;
> unsigned i;
>
> @@ -994,7 +996,6 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
>
> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
> - uint32_t req = hub->get_invalidate_req(vm_id);
>
> amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
> amdgpu_ring_write(ring,
> --
> 2.5.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 8/8] drm/amdgpu: cleanup VMHUB bit definitions
[not found] ` <CADnq5_M+jYQU6Utw8OrLeFurwsnw=5Y1EdgwXGnhBDrqtszhcQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2017-04-04 7:31 ` Christian König
0 siblings, 0 replies; 13+ messages in thread
From: Christian König @ 2017-04-04 7:31 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
Am 03.04.2017 um 21:31 schrieb Alex Deucher:
> On Mon, Apr 3, 2017 at 8:39 AM, Christian König <deathsimple@vodafone.de> wrote:
>> From: Christian König <christian.koenig@amd.com>
>>
>> The two hubs are just instances of the same hardware,
>> so the register bits are identical.
> Removing get_vm_protection_bits makes sense since those are limited to
> the gmc module. I'd prefer to keep get_invalidation_req since that
> protects the ip modules from a direct dependency on gmc9. We'd end up
> reimplementing this when we come to an ip module that ends up being
> used on a chip with a newer gmc. Also seems cleaner this way in my
> opinion.
In this case let's move the callback into the mc/gart function pointers.
The crux is that we need to change those settings when we improve the VM
flushing, and I really don't want to do all changes twice.
Christian.
>
> Alex
>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 --------------------------------
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 33 +++++++++++++++++++++++++++-----
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 2 ++
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33 --------------------------------
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 5 +++--
>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 ++-
>> 9 files changed, 39 insertions(+), 78 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index cc43fee..f6f6dcb 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -572,8 +572,6 @@ struct amdgpu_vmhub {
>> uint32_t vm_context0_cntl;
>> uint32_t vm_l2_pro_fault_status;
>> uint32_t vm_l2_pro_fault_cntl;
>> - uint32_t (*get_invalidate_req)(unsigned int vm_id);
>> - uint32_t (*get_vm_protection_bits)(void);
>> };
>>
>> /*
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index c8a1c4e..4ae5ac0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -36,6 +36,7 @@
>> #include "soc15_common.h"
>> #include "clearstate_gfx9.h"
>> #include "v9_structs.h"
>> +#include "gmc_v9_0.h"
>>
>> #define GFX9_NUM_GFX_RINGS 1
>> #define GFX9_NUM_COMPUTE_RINGS 8
>> @@ -3148,6 +3149,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>> unsigned vm_id, uint64_t pd_addr)
>> {
>> int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
>> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
>> unsigned eng = ring->idx;
>> unsigned i;
>>
>> @@ -3157,7 +3159,6 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
>> - uint32_t req = hub->get_invalidate_req(vm_id);
>>
>> gfx_v9_0_write_data_to_reg(ring, usepfp, true,
>> hub->ctx0_ptb_addr_lo32
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> index dd48637..0abb128 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> @@ -299,36 +299,6 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
>> WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
>> }
>>
>> -static uint32_t gfxhub_v1_0_get_invalidate_req(unsigned int vm_id)
>> -{
>> - u32 req = 0;
>> -
>> - /* invalidate using legacy mode on vm_id*/
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> - PER_VMID_INVALIDATE_REQ, 1 << vm_id);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> - CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
>> -
>> - return req;
>> -}
>> -
>> -static uint32_t gfxhub_v1_0_get_vm_protection_bits(void)
>> -{
>> - return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
>> -}
>> -
>> static int gfxhub_v1_0_early_init(void *handle)
>> {
>> return 0;
>> @@ -361,9 +331,6 @@ static int gfxhub_v1_0_sw_init(void *handle)
>> hub->vm_l2_pro_fault_cntl =
>> SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
>>
>> - hub->get_invalidate_req = gfxhub_v1_0_get_invalidate_req;
>> - hub->get_vm_protection_bits = gfxhub_v1_0_get_vm_protection_bits;
>> -
>> return 0;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index 268cedb..43b429e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -75,11 +75,18 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>> struct amdgpu_vmhub *hub;
>> u32 tmp, reg, bits, i;
>>
>> + bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> + VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
>> +
>> switch (state) {
>> case AMDGPU_IRQ_STATE_DISABLE:
>> /* MM HUB */
>> hub = &adev->vmhub[AMDGPU_MMHUB];
>> - bits = hub->get_vm_protection_bits();
>> for (i = 0; i< 16; i++) {
>> reg = hub->vm_context0_cntl + i;
>> tmp = RREG32(reg);
>> @@ -89,7 +96,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>>
>> /* GFX HUB */
>> hub = &adev->vmhub[AMDGPU_GFXHUB];
>> - bits = hub->get_vm_protection_bits();
>> for (i = 0; i < 16; i++) {
>> reg = hub->vm_context0_cntl + i;
>> tmp = RREG32(reg);
>> @@ -100,7 +106,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>> case AMDGPU_IRQ_STATE_ENABLE:
>> /* MM HUB */
>> hub = &adev->vmhub[AMDGPU_MMHUB];
>> - bits = hub->get_vm_protection_bits();
>> for (i = 0; i< 16; i++) {
>> reg = hub->vm_context0_cntl + i;
>> tmp = RREG32(reg);
>> @@ -110,7 +115,6 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>>
>> /* GFX HUB */
>> hub = &adev->vmhub[AMDGPU_GFXHUB];
>> - bits = hub->get_vm_protection_bits();
>> for (i = 0; i < 16; i++) {
>> reg = hub->vm_context0_cntl + i;
>> tmp = RREG32(reg);
>> @@ -169,6 +173,25 @@ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
>> adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
>> }
>>
>> +uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
>> +{
>> + u32 req = 0;
>> +
>> + /* invalidate using legacy mode on vm_id*/
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> + PER_VMID_INVALIDATE_REQ, 1 << vm_id);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
>> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
>> +
>> + return req;
>> +}
>> +
>> /*
>> * GART
>> * VMID 0 is the physical GPU addresses as used by the kernel.
>> @@ -198,7 +221,7 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &adev->vmhub[i];
>> - u32 tmp = hub->get_invalidate_req(vmid);
>> + u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
>>
>> WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>> index b030ca5..ea046a8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>> @@ -27,4 +27,6 @@
>> extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
>> extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
>>
>> +uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id);
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> index c1dc8c4..6cd1c55 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> @@ -317,36 +317,6 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
>> WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
>> }
>>
>> -static uint32_t mmhub_v1_0_get_invalidate_req(unsigned int vm_id)
>> -{
>> - u32 req = 0;
>> -
>> - /* invalidate using legacy mode on vm_id*/
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> - PER_VMID_INVALIDATE_REQ, 1 << vm_id);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
>> - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
>> - CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
>> -
>> - return req;
>> -}
>> -
>> -static uint32_t mmhub_v1_0_get_vm_protection_bits(void)
>> -{
>> - return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>> - VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
>> -}
>> -
>> static int mmhub_v1_0_early_init(void *handle)
>> {
>> return 0;
>> @@ -379,9 +349,6 @@ static int mmhub_v1_0_sw_init(void *handle)
>> hub->vm_l2_pro_fault_cntl =
>> SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
>>
>> - hub->get_invalidate_req = mmhub_v1_0_get_invalidate_req;
>> - hub->get_vm_protection_bits = mmhub_v1_0_get_vm_protection_bits;
>> -
>> return 0;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index 6cfb100..e30ea26 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -39,6 +39,7 @@
>> #include "soc15_common.h"
>> #include "soc15.h"
>> #include "vega10_sdma_pkt_open.h"
>> +#include "gmc_v9_0.h"
>>
>> MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
>> MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
>> @@ -1039,6 +1040,7 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
>> static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>> unsigned vm_id, uint64_t pd_addr)
>> {
>> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
>> unsigned eng = ring->idx;
>> unsigned i;
>>
>> @@ -1048,7 +1050,6 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
>> - uint32_t req = hub->get_invalidate_req(vm_id);
>>
>> amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
>> SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> index 3457546..593b04b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> @@ -27,6 +27,7 @@
>> #include "amdgpu_uvd.h"
>> #include "soc15d.h"
>> #include "soc15_common.h"
>> +#include "gmc_v9_0.h"
>>
>> #include "vega10/soc15ip.h"
>> #include "vega10/UVD/uvd_7_0_offset.h"
>> @@ -1045,6 +1046,7 @@ static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
>> static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>> unsigned vm_id, uint64_t pd_addr)
>> {
>> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
>> uint32_t data0, data1, mask;
>> unsigned eng = ring->idx;
>> unsigned i;
>> @@ -1055,7 +1057,6 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
>> - uint32_t req = hub->get_invalidate_req(vm_id);
>>
>> data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
>> data1 = upper_32_bits(pd_addr);
>> @@ -1091,6 +1092,7 @@ static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
>> static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>> unsigned int vm_id, uint64_t pd_addr)
>> {
>> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
>> unsigned eng = ring->idx;
>> unsigned i;
>>
>> @@ -1100,7 +1102,6 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
>> - uint32_t req = hub->get_invalidate_req(vm_id);
>>
>> amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
>> amdgpu_ring_write(ring,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> index ad5fd98..9c5ce91 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> @@ -31,6 +31,7 @@
>> #include "soc15d.h"
>> #include "soc15_common.h"
>> #include "mmsch_v1_0.h"
>> +#include "gmc_v9_0.h"
>>
>> #include "vega10/soc15ip.h"
>> #include "vega10/VCE/vce_4_0_offset.h"
>> @@ -985,6 +986,7 @@ static void vce_v4_0_ring_insert_end(struct amdgpu_ring *ring)
>> static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
>> unsigned int vm_id, uint64_t pd_addr)
>> {
>> + uint32_t req = gmc_v9_0_get_invalidate_req(vm_id);
>> unsigned eng = ring->idx;
>> unsigned i;
>>
>> @@ -994,7 +996,6 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
>>
>> for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>> struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
>> - uint32_t req = hub->get_invalidate_req(vm_id);
>>
>> amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
>> amdgpu_ring_write(ring,
>> --
>> 2.5.0
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/8] drm/amdgpu: fix VMHUB order to match the hardware
[not found] ` <CADnq5_NHtW=w2YfZw4=3G-rsYRyxyGJ0NPRormJtB6p+BqUjfg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2017-04-05 2:37 ` Zhang, Jerry (Junwei)
0 siblings, 0 replies; 13+ messages in thread
From: Zhang, Jerry (Junwei) @ 2017-04-05 2:37 UTC (permalink / raw)
To: Alex Deucher, Christian König; +Cc: amd-gfx list
On 04/04/2017 03:23 AM, Alex Deucher wrote:
> On Mon, Apr 3, 2017 at 8:39 AM, Christian König <deathsimple@vodafone.de> wrote:
>> From: Christian König <christian.koenig@amd.com>
>>
>> Match our defines with what the hw uses.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>
> Patches 1-4, 6-7:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
With the Alex's comments.
Patches 1~7:
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
(Although it looks they were already landed)
Jerry
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++---------
>> 2 files changed, 5 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 86fba1a..c156534 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -126,8 +126,8 @@ extern int amdgpu_param_buf_per_se;
>>
>> /* max number of VMHUB */
>> #define AMDGPU_MAX_VMHUBS 2
>> -#define AMDGPU_MMHUB 0
>> -#define AMDGPU_GFXHUB 1
>> +#define AMDGPU_GFXHUB 0
>> +#define AMDGPU_MMHUB 1
>>
>> /* hardcode that limit for now */
>> #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index df69aae..8dd99b2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -129,8 +129,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
>> struct amdgpu_irq_src *source,
>> struct amdgpu_iv_entry *entry)
>> {
>> - struct amdgpu_vmhub *gfxhub = &adev->vmhub[AMDGPU_GFXHUB];
>> - struct amdgpu_vmhub *mmhub = &adev->vmhub[AMDGPU_MMHUB];
>> + struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
>> uint32_t status = 0;
>> u64 addr;
>>
>> @@ -138,13 +137,8 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
>> addr |= ((u64)entry->src_data[1] & 0xf) << 44;
>>
>> if (!amdgpu_sriov_vf(adev)) {
>> - if (entry->vm_id_src) {
>> - status = RREG32(mmhub->vm_l2_pro_fault_status);
>> - WREG32_P(mmhub->vm_l2_pro_fault_cntl, 1, ~1);
>> - } else {
>> - status = RREG32(gfxhub->vm_l2_pro_fault_status);
>> - WREG32_P(gfxhub->vm_l2_pro_fault_cntl, 1, ~1);
>> - }
>> + status = RREG32(hub->vm_l2_pro_fault_status);
>> + WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
>> }
>>
>> if (printk_ratelimit()) {
>> --
>> 2.5.0
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2017-04-05 2:37 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-03 12:39 [PATCH 1/8] drm/amdgpu: fix VMHUB order to match the hardware Christian König
[not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-03 12:39 ` [PATCH 2/8] drm/amdgpu: move VM related defines into amdgpu_vm.h Christian König
2017-04-03 12:39 ` [PATCH 3/8] drm/amdgpu: remove VMID first tracking Christian König
2017-04-03 12:39 ` [PATCH 4/8] drm/amdgpu: coding style of amdgpu_vm_is_gpu_reset Christian König
2017-04-03 12:39 ` [PATCH 5/8] drm/amdgpu: cleanup coding style in amdgpu_vm_flush Christian König
[not found] ` <1491223199-28892-5-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-03 19:18 ` Alex Deucher
2017-04-03 12:39 ` [PATCH 6/8] drm/amdgpu: cleanup logic " Christian König
2017-04-03 12:39 ` [PATCH 7/8] drm/amdgpu: move adjust_mc_addr into amdgpu_gart_funcs Christian König
2017-04-03 12:39 ` [PATCH 8/8] drm/amdgpu: cleanup VMHUB bit definitions Christian König
[not found] ` <1491223199-28892-8-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-03 19:31 ` Alex Deucher
[not found] ` <CADnq5_M+jYQU6Utw8OrLeFurwsnw=5Y1EdgwXGnhBDrqtszhcQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-04 7:31 ` Christian König
2017-04-03 19:23 ` [PATCH 1/8] drm/amdgpu: fix VMHUB order to match the hardware Alex Deucher
[not found] ` <CADnq5_NHtW=w2YfZw4=3G-rsYRyxyGJ0NPRormJtB6p+BqUjfg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-05 2:37 ` Zhang, Jerry (Junwei)
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