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From: "Christian König" <deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [PATCH 5/8] drm/amdgpu: cleanup coding style in amdgpu_vm_flush
Date: Mon,  3 Apr 2017 14:39:56 +0200	[thread overview]
Message-ID: <1491223199-28892-5-git-send-email-deathsimple@vodafone.de> (raw)
In-Reply-To: <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>

From: Christian König <christian.koenig@amd.com>

The indentation was of in more than one place.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 88 +++++++++++++++++-----------------
 1 file changed, 45 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 4ffd2244..85e45b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -597,60 +597,62 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
 		id->gws_size != job->gws_size ||
 		id->oa_base != job->oa_base ||
 		id->oa_size != job->oa_size);
+	unsigned patch_offset = 0;
 	int r;
 
-	if (job->vm_needs_flush || gds_switch_needed ||
-		amdgpu_vm_had_gpu_reset(adev, id) ||
-		amdgpu_vm_ring_has_compute_vm_bug(ring)) {
-		unsigned patch_offset = 0;
+	if (!job->vm_needs_flush && !gds_switch_needed &&
+	    !amdgpu_vm_had_gpu_reset(adev, id) &&
+	    !amdgpu_vm_ring_has_compute_vm_bug(ring))
+		return 0;
 
-		if (ring->funcs->init_cond_exec)
-			patch_offset = amdgpu_ring_init_cond_exec(ring);
 
-		if (ring->funcs->emit_pipeline_sync &&
-			(job->vm_needs_flush || gds_switch_needed ||
-			amdgpu_vm_ring_has_compute_vm_bug(ring)))
-			amdgpu_ring_emit_pipeline_sync(ring);
+	if (ring->funcs->init_cond_exec)
+		patch_offset = amdgpu_ring_init_cond_exec(ring);
 
-		if (ring->funcs->emit_vm_flush && (job->vm_needs_flush ||
-			amdgpu_vm_had_gpu_reset(adev, id))) {
-			struct fence *fence;
-			u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
+	if (ring->funcs->emit_pipeline_sync &&
+	    (job->vm_needs_flush || gds_switch_needed ||
+	     amdgpu_vm_ring_has_compute_vm_bug(ring)))
+		amdgpu_ring_emit_pipeline_sync(ring);
 
-			trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
-			amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
+	if (ring->funcs->emit_vm_flush &&
+	    (job->vm_needs_flush || amdgpu_vm_had_gpu_reset(adev, id))) {
 
-			r = amdgpu_fence_emit(ring, &fence);
-			if (r)
-				return r;
+		u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
+		struct fence *fence;
 
-			mutex_lock(&adev->vm_manager.lock);
-			fence_put(id->last_flush);
-			id->last_flush = fence;
-			mutex_unlock(&adev->vm_manager.lock);
-		}
+		trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
+		amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
 
-		if (gds_switch_needed) {
-			id->gds_base = job->gds_base;
-			id->gds_size = job->gds_size;
-			id->gws_base = job->gws_base;
-			id->gws_size = job->gws_size;
-			id->oa_base = job->oa_base;
-			id->oa_size = job->oa_size;
-			amdgpu_ring_emit_gds_switch(ring, job->vm_id,
-							job->gds_base, job->gds_size,
-							job->gws_base, job->gws_size,
-							job->oa_base, job->oa_size);
-		}
+		r = amdgpu_fence_emit(ring, &fence);
+		if (r)
+			return r;
 
-		if (ring->funcs->patch_cond_exec)
-			amdgpu_ring_patch_cond_exec(ring, patch_offset);
+		mutex_lock(&adev->vm_manager.lock);
+		fence_put(id->last_flush);
+		id->last_flush = fence;
+		mutex_unlock(&adev->vm_manager.lock);
+	}
 
-		/* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
-		if (ring->funcs->emit_switch_buffer) {
-			amdgpu_ring_emit_switch_buffer(ring);
-			amdgpu_ring_emit_switch_buffer(ring);
-		}
+	if (gds_switch_needed) {
+		id->gds_base = job->gds_base;
+		id->gds_size = job->gds_size;
+		id->gws_base = job->gws_base;
+		id->gws_size = job->gws_size;
+		id->oa_base = job->oa_base;
+		id->oa_size = job->oa_size;
+		amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base,
+					    job->gds_size, job->gws_base,
+					    job->gws_size, job->oa_base,
+					    job->oa_size);
+	}
+
+	if (ring->funcs->patch_cond_exec)
+		amdgpu_ring_patch_cond_exec(ring, patch_offset);
+
+	/* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
+	if (ring->funcs->emit_switch_buffer) {
+		amdgpu_ring_emit_switch_buffer(ring);
+		amdgpu_ring_emit_switch_buffer(ring);
 	}
 	return 0;
 }
-- 
2.5.0

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  parent reply	other threads:[~2017-04-03 12:39 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-03 12:39 [PATCH 1/8] drm/amdgpu: fix VMHUB order to match the hardware Christian König
     [not found] ` <1491223199-28892-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-03 12:39   ` [PATCH 2/8] drm/amdgpu: move VM related defines into amdgpu_vm.h Christian König
2017-04-03 12:39   ` [PATCH 3/8] drm/amdgpu: remove VMID first tracking Christian König
2017-04-03 12:39   ` [PATCH 4/8] drm/amdgpu: coding style of amdgpu_vm_is_gpu_reset Christian König
2017-04-03 12:39   ` Christian König [this message]
     [not found]     ` <1491223199-28892-5-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-03 19:18       ` [PATCH 5/8] drm/amdgpu: cleanup coding style in amdgpu_vm_flush Alex Deucher
2017-04-03 12:39   ` [PATCH 6/8] drm/amdgpu: cleanup logic " Christian König
2017-04-03 12:39   ` [PATCH 7/8] drm/amdgpu: move adjust_mc_addr into amdgpu_gart_funcs Christian König
2017-04-03 12:39   ` [PATCH 8/8] drm/amdgpu: cleanup VMHUB bit definitions Christian König
     [not found]     ` <1491223199-28892-8-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-03 19:31       ` Alex Deucher
     [not found]         ` <CADnq5_M+jYQU6Utw8OrLeFurwsnw=5Y1EdgwXGnhBDrqtszhcQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-04  7:31           ` Christian König
2017-04-03 19:23   ` [PATCH 1/8] drm/amdgpu: fix VMHUB order to match the hardware Alex Deucher
     [not found]     ` <CADnq5_NHtW=w2YfZw4=3G-rsYRyxyGJ0NPRormJtB6p+BqUjfg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-05  2:37       ` Zhang, Jerry (Junwei)

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