Device Tree Binding for Intel FPGA Video and Image Processing Suite

Device Tree Binding for Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

[-- Attachment #1: Type: text/plain, Size: 505 bytes --]

Hi Rob,

I would like to upstream the attached device tree binding patch to the
community. This is required for the support of framebuffer drivers of
the Intel FPGA Video and Image Processing Suite intended for the
Arria10 devkit.

The device tree information includes the maximum width and height
supported by the framebuffer display. These are fixed parameters
determined by the use who the Quartus design system to program the
FPGA in the Arria10 devkit and its variants.

BR

Hean Loong

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-Intel-FPGA-Video-and-Image-Processing-Suite-device-t.patch --]
[-- Type: text/x-patch; name="0001-Intel-FPGA-Video-and-Image-Processing-Suite-device-t.patch", Size: 1918 bytes --]

From 23a9e274bb517b8e232c5aa4cf9737de1644b708 Mon Sep 17 00:00:00 2001
From: Ong, Hean Loong <hean.loong.ong@intel.com>
Date: Thu, 30 Mar 2017 17:59:37 +0800
Subject: [PATCHv0] Intel FPGA Video and Image Processing Suite device tree binding

	Device tree binding for Intel FPGA Video and Image
	Processing Suite. The binding involved would be generated
	from the Altera (Intel) Qsys system. The bindings would
	set the max width, max height, buts per pixel and memory
	port width. The device tree binding only supports the Intel
	Arria10 devkit and its variants. Vendor name retained as
	altr.

Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
---
 .../devicetree/bindings/gpu/altr,vip-fb2.txt       |   24 ++++++++++++++++++++
 1 files changed, 24 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt

diff --git a/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
new file mode 100644
index 0000000..9ba3209
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
@@ -0,0 +1,24 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware:  Arria 10 and above with display port IP
+
+Required properties:
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer controller's
+  registers.
+- max-width: The width of the framebuffer in pixels.
+- max-height: The height of the framebuffer in pixels.
+- bits-per-symbol: only "8" is currently supported
+- mem-port-width = the bus width of the avalon master port on the frame reader
+
+Example:
+
+dp_0_frame_buf: vip@0x100000280 {
+	compatible = "altr,vip-frame-buffer-2.0";
+	reg = <0x00000001 0x00000280 0x00000040>;
+	altr,max-width = <1280>;
+	altr,max-height = <720>;
+	altr,bits-per-symbol = <8>;
+	altr,mem-port-width = <128>;
+};
+
-- 
1.7.1

Re: Device Tree Binding for Intel FPGA Video and Image Processing Suite

[Rob Herring]

On Fri, Mar 31, 2017 at 3:50 AM, Ong, Hean Loong
<hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> wrote:
> Hi Rob,
>
> I would like to upstream the attached device tree binding patch to the
> community. This is required for the support of framebuffer drivers of
> the Intel FPGA Video and Image Processing Suite intended for the
> Arria10 devkit.
>
> The device tree information includes the maximum width and height
> supported by the framebuffer display. These are fixed parameters
> determined by the use who the Quartus design system to program the
> FPGA in the Arria10 devkit and its variants.

Please read Documentation/devicetree/bindings/submitting-patches.txt.

The first problem is sending the patch as an attachment.

Rob
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: Device Tree Binding for Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

Hi Rob,

Apologies for the mistake. Below are the bindings

From 23a9e274bb517b8e232c5aa4cf9737de1644b708 Mon Sep 17 00:00:00 2001
From: Ong, Hean Loong <hean.loong.ong@intel.com>
Date: Thu, 30 Mar 2017 17:59:37 +0800
Subject: [PATCHv0] Intel FPGA Video and Image Processing Suite device tree binding

        Device tree binding for Intel FPGA Video and Image
        Processing Suite. The binding involved would be generated
        from the Altera (Intel) Qsys system. The bindings would
        set the max width, max height, buts per pixel and memory
        port width. The device tree binding only supports the Intel
        Arria10 devkit and its variants. Vendor name retained as
        altr.

Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
---
 .../devicetree/bindings/gpu/altr,vip-fb2.txt       |   24 ++++++++++++++++++++
 1 files changed, 24 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt

diff --git a/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
new file mode 100644
index 0000000..9ba3209
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
@@ -0,0 +1,24 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware:  Arria 10 and above with display port IP
+
+Required properties:
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer controller's
+  registers.
+- max-width: The width of the framebuffer in pixels.
+- max-height: The height of the framebuffer in pixels.
+- bits-per-symbol: only "8" is currently supported
+- mem-port-width = the bus width of the avalon master port on the frame reader
+
+Example:
+
+dp_0_frame_buf: vip@0x100000280 {
+       compatible = "altr,vip-frame-buffer-2.0";
+       reg = <0x00000001 0x00000280 0x00000040>;
+       altr,max-width = <1280>;
+       altr,max-height = <720>;
+       altr,bits-per-symbol = <8>;
+       altr,mem-port-width = <128>;
+};
+
-- 
1.7.1

Re: Device Tree Binding for Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

Hi Rob,

Any comments on the patch?

BR 

Hean Loong

On Tue, 2017-04-04 at 03:57 +0000, Ong, Hean Loong wrote:
> Hi Rob,
> 
> Apologies for the mistake. Below are the bindings
> 
> From 23a9e274bb517b8e232c5aa4cf9737de1644b708 Mon Sep 17 00:00:00
> 2001
> From: Ong, Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> Date: Thu, 30 Mar 2017 17:59:37 +0800
> Subject: [PATCHv0] Intel FPGA Video and Image Processing Suite device
> tree binding
> 
>         Device tree binding for Intel FPGA Video and Image
>         Processing Suite. The binding involved would be generated
>         from the Altera (Intel) Qsys system. The bindings would
>         set the max width, max height, buts per pixel and memory
>         port width. The device tree binding only supports the Intel
>         Arria10 devkit and its variants. Vendor name retained as
>         altr.
> 
> Signed-off-by: Ong, Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> ---
>  .../devicetree/bindings/gpu/altr,vip-fb2.txt       |   24
> ++++++++++++++++++++
>  1 files changed, 24 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpu/altr,vip-
> fb2.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
> b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
> new file mode 100644
> index 0000000..9ba3209
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
> @@ -0,0 +1,24 @@
> +Intel Video and Image Processing(VIP) Frame Buffer II bindings
> +
> +Supported hardware:  Arria 10 and above with display port IP
> +
> +Required properties:
> +- compatible: "altr,vip-frame-buffer-2.0"
> +- reg: Physical base address and length of the framebuffer
> controller's
> +  registers.
> +- max-width: The width of the framebuffer in pixels.
> +- max-height: The height of the framebuffer in pixels.
> +- bits-per-symbol: only "8" is currently supported
> +- mem-port-width = the bus width of the avalon master port on the
> frame reader
> +
> +Example:
> +
> +dp_0_frame_buf: vip@0x100000280 {
> +       compatible = "altr,vip-frame-buffer-2.0";
> +       reg = <0x00000001 0x00000280 0x00000040>;
> +       altr,max-width = <1280>;
> +       altr,max-height = <720>;
> +       altr,bits-per-symbol = <8>;
> +       altr,mem-port-width = <128>;
> +};
> +
> -- 
> 1.7.1
> 
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: Device Tree Binding for Intel FPGA Video and Image Processing Suite

[Rob Herring]

On Thu, Apr 6, 2017 at 1:42 AM, Ong, Hean Loong
<hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> wrote:
> Hi Rob,
>
> Any comments on the patch?

Yes, the same ones I provided 5 months ago to you. Repeated below.

>
> BR
>
> Hean Loong
>
> On Tue, 2017-04-04 at 03:57 +0000, Ong, Hean Loong wrote:
>> Hi Rob,
>>
>> Apologies for the mistake. Below are the bindings
>>
>> From 23a9e274bb517b8e232c5aa4cf9737de1644b708 Mon Sep 17 00:00:00
>> 2001
>> From: Ong, Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>> Date: Thu, 30 Mar 2017 17:59:37 +0800
>> Subject: [PATCHv0] Intel FPGA Video and Image Processing Suite device
>> tree binding

This is still not how you email patches. The easiest way is git-send-email.

>>         Device tree binding for Intel FPGA Video and Image
>>         Processing Suite. The binding involved would be generated
>>         from the Altera (Intel) Qsys system. The bindings would
>>         set the max width, max height, buts per pixel and memory
>>         port width. The device tree binding only supports the Intel
>>         Arria10 devkit and its variants. Vendor name retained as
>>         altr.

There should be no indentation here.

>>
>> Signed-off-by: Ong, Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>> ---
>>  .../devicetree/bindings/gpu/altr,vip-fb2.txt       |   24
>> ++++++++++++++++++++

bindings/display/. This is not a GPU.

>>  1 files changed, 24 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/gpu/altr,vip-
>> fb2.txt
>>
>> diff --git a/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
>> b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
>> new file mode 100644
>> index 0000000..9ba3209
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
>> @@ -0,0 +1,24 @@
>> +Intel Video and Image Processing(VIP) Frame Buffer II bindings
>> +
>> +Supported hardware:  Arria 10 and above with display port IP
>> +
>> +Required properties:
>> +- compatible: "altr,vip-frame-buffer-2.0"
>> +- reg: Physical base address and length of the framebuffer
>> controller's
>> +  registers.

>> +- max-width: The width of the framebuffer in pixels.
>> +- max-height: The height of the framebuffer in pixels.
>> +- bits-per-symbol: only "8" is currently supported

Why do these need to be in DT?

>> +- mem-port-width = the bus width of the avalon master port on the
>> frame reader

Still needs a vendor prefix.

>> +
>> +Example:
>> +
>> +dp_0_frame_buf: vip@0x100000280 {

display-controller@100000280

>> +       compatible = "altr,vip-frame-buffer-2.0";
>> +       reg = <0x00000001 0x00000280 0x00000040>;
>> +       altr,max-width = <1280>;
>> +       altr,max-height = <720>;
>> +       altr,bits-per-symbol = <8>;
>> +       altr,mem-port-width = <128>;
>> +};
>> +
>> --
>> 1.7.1
>>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: Device Tree Binding for Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

Hi,

First of all thank you Rob for your time and patience. Especially on how this patch was sent out. I would ensure it would not happen again for the subsequent patches. 

On the issue of why the DT has certain resolution fixed is due to the fact that our Quartus system generates these attributes in according to the specific display resolution as desired by the user. The values here are the ideal resolution supported by the hardware for the reference design. 

On the other hand my bad on the vendor prefix as I misunderstood the "altr," as the vendor prefix

Thanks

Hean Loong

>-----Original Message-----
>From: Rob Herring [mailto:robh+dt@kernel.org]
>Sent: Saturday, April 8, 2017 5:53 AM
>To: Ong, Hean Loong <hean.loong.ong@intel.com>
>Cc: devicetree@vger.kernel.org
>Subject: Re: Device Tree Binding for Intel FPGA Video and Image Processing Suite
>
>On Thu, Apr 6, 2017 at 1:42 AM, Ong, Hean Loong <hean.loong.ong@intel.com>
>wrote:
>> Hi Rob,
>>
>> Any comments on the patch?
>
>Yes, the same ones I provided 5 months ago to you. Repeated below.
>
>>
>> BR
>>
>> Hean Loong
>>
>> On Tue, 2017-04-04 at 03:57 +0000, Ong, Hean Loong wrote:
>>> Hi Rob,
>>>
>>> Apologies for the mistake. Below are the bindings
>>>
>>> From 23a9e274bb517b8e232c5aa4cf9737de1644b708 Mon Sep 17 00:00:00
>>> 2001
>>> From: Ong, Hean Loong <hean.loong.ong@intel.com>
>>> Date: Thu, 30 Mar 2017 17:59:37 +0800
>>> Subject: [PATCHv0] Intel FPGA Video and Image Processing Suite device
>>> tree binding
>
>This is still not how you email patches. The easiest way is git-send-email.
>
>>>         Device tree binding for Intel FPGA Video and Image
>>>         Processing Suite. The binding involved would be generated
>>>         from the Altera (Intel) Qsys system. The bindings would
>>>         set the max width, max height, buts per pixel and memory
>>>         port width. The device tree binding only supports the Intel
>>>         Arria10 devkit and its variants. Vendor name retained as
>>>         altr.
>
>There should be no indentation here.
>
>>>
>>> Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
>>> ---
>>>  .../devicetree/bindings/gpu/altr,vip-fb2.txt       |   24
>>> ++++++++++++++++++++
>
>bindings/display/. This is not a GPU.
>
>>>  1 files changed, 24 insertions(+), 0 deletions(-)  create mode
>>> 100644 Documentation/devicetree/bindings/gpu/altr,vip-
>>> fb2.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
>>> b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
>>> new file mode 100644
>>> index 0000000..9ba3209
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
>>> @@ -0,0 +1,24 @@
>>> +Intel Video and Image Processing(VIP) Frame Buffer II bindings
>>> +
>>> +Supported hardware:  Arria 10 and above with display port IP
>>> +
>>> +Required properties:
>>> +- compatible: "altr,vip-frame-buffer-2.0"
>>> +- reg: Physical base address and length of the framebuffer
>>> controller's
>>> +  registers.
>
>>> +- max-width: The width of the framebuffer in pixels.
>>> +- max-height: The height of the framebuffer in pixels.
>>> +- bits-per-symbol: only "8" is currently supported
>
>Why do these need to be in DT?
>
>>> +- mem-port-width = the bus width of the avalon master port on the
>>> frame reader
>
>Still needs a vendor prefix.
>
>>> +
>>> +Example:
>>> +
>>> +dp_0_frame_buf: vip@0x100000280 {
>
>display-controller@100000280
>
>>> +       compatible = "altr,vip-frame-buffer-2.0";
>>> +       reg = <0x00000001 0x00000280 0x00000040>;
>>> +       altr,max-width = <1280>;
>>> +       altr,max-height = <720>;
>>> +       altr,bits-per-symbol = <8>;
>>> +       altr,mem-port-width = <128>;
>>> +};
>>> +
>>> --
>>> 1.7.1
>>>

Device Tree Binding for Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

Hi Rob,

I am resubmitting the patch again since the last doesn't comply with
the rules of the community.

>From 23a9e274bb517b8e232c5aa4cf9737de1644b708 Mon Sep 17 00:00:00 2001
From: Ong, Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Date: Thu, 30 Mar 2017 17:59:37 +0800
Subject: [PATCHv0] Intel FPGA Video and Image Processing Suite device
tree binding

        Device tree binding for Intel FPGA Video and Image
        Processing Suite. The binding involved would be generated
        from the Altera (Intel) Qsys system. The bindings would
        set the max width, max height, buts per pixel and memory
        port width. The device tree binding only supports the Intel
        Arria10 devkit and its variants. Vendor name retained as
        altr.

Signed-off-by: Ong, Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
 .../devicetree/bindings/gpu/altr,vip-fb2.txt       |   24
++++++++++++++++++++
 1 files changed, 24 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpu/altr,vip-
fb2.txt

diff --git a/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
new file mode 100644
index 0000000..9ba3209
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
@@ -0,0 +1,24 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware:  Arria 10 and above with display port IP
+
+Required properties:
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer
controller's
+  registers.
+- max-width: The width of the framebuffer in pixels.
+- max-height: The height of the framebuffer in pixels.
+- bits-per-symbol: only "8" is currently supported
+- mem-port-width = the bus width of the avalon master port on the
frame reader
+
+Example:
+
+dp_0_frame_buf: vip@0x100000280 {
+       compatible = "altr,vip-frame-buffer-2.0";
+       reg = <0x00000001 0x00000280 0x00000040>;
+       altr,max-width = <1280>;
+       altr,max-height = <720>;
+       altr,bits-per-symbol = <8>;
+       altr,mem-port-width = <128>;
+};
+
-- 
1.7.1

-- 
BR

Hean-Loong
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html