From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933480AbdDHAfL (ORCPT ); Fri, 7 Apr 2017 20:35:11 -0400 Received: from mga02.intel.com ([134.134.136.20]:43565 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753691AbdDHAdi (ORCPT ); Fri, 7 Apr 2017 20:33:38 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,168,1488873600"; d="scan'208";a="71280008" From: Vikas Shivappa To: vikas.shivappa@intel.com, x86@kernel.org, linux-kernel@vger.kernel.org Cc: hpa@zytor.com, tglx@linutronix.de, mingo@kernel.org, ravi.v.shankar@intel.com, tony.luck@intel.com, fenghua.yu@intel.com, vikas.shivappa@linux.intel.com Subject: [PATCH 8/8] x86/intel_rdt/mba: Add schemata file support for MBA Date: Fri, 7 Apr 2017 17:33:57 -0700 Message-Id: <1491611637-20417-9-git-send-email-vikas.shivappa@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491611637-20417-1-git-send-email-vikas.shivappa@linux.intel.com> References: <1491611637-20417-1-git-send-email-vikas.shivappa@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support to update the MBA bandwidth values for the domains. The MBA bandwidth values are specified by updating the schemata. We do the following to parse the bandwidth(bw) value from schemata and update the PQOS_MSRS: 1. check the bw to satisfy the minimum and max bandwidth requirements. 2. To meet the granularity requirement intermediate values are rounded to the next control step available on the hardware. 3. map the bw to delay values and write the delay values to corresponding domain PQOS_MSRs which are indexed from 0xD50. For linear scale the delay value = 100 - bw. Currently no Intel SKUs support non-linear delay values. Signed-off-by: Vikas Shivappa --- arch/x86/include/asm/intel_rdt.h | 1 + arch/x86/kernel/cpu/intel_rdt.c | 2 ++ arch/x86/kernel/cpu/intel_rdt_schemata.c | 46 ++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h index 63fa034..32fbb28 100644 --- a/arch/x86/include/asm/intel_rdt.h +++ b/arch/x86/include/asm/intel_rdt.h @@ -169,6 +169,7 @@ struct rdt_resource { void rdt_get_cache_infofile(struct rdt_resource *r); void rdt_get_mba_infofile(struct rdt_resource *r); int parse_cbm(char *buf, struct rdt_resource *r, struct rdt_domain *d); +int parse_bw(char *buf, struct rdt_resource *r, struct rdt_domain *d); extern struct mutex rdtgroup_mutex; diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c index 695870a..fbbe0c7 100644 --- a/arch/x86/kernel/cpu/intel_rdt.c +++ b/arch/x86/kernel/cpu/intel_rdt.c @@ -106,7 +106,9 @@ struct rdt_resource rdt_resources_all[] = { .name = "MB", .domains = domain_init(RDT_RESOURCE_MBA), .msr_base = IA32_MBA_THRTL_BASE, + .parse_ctrlval = parse_bw, .msr_update = mba_wrmsr, + .format_str = "%d=%*d", .cache_level = 3, .cbm_idx_multi = 1, .cbm_idx_offset = 0 diff --git a/arch/x86/kernel/cpu/intel_rdt_schemata.c b/arch/x86/kernel/cpu/intel_rdt_schemata.c index 03f9a70..9154695 100644 --- a/arch/x86/kernel/cpu/intel_rdt_schemata.c +++ b/arch/x86/kernel/cpu/intel_rdt_schemata.c @@ -29,6 +29,52 @@ #include /* + * Check whether MBA bandwidth percentage value is correct. + * The value is checked against the minimum and max bandwidth + * values specified by the hardware. The allocated b/w + * percentage is rounded off the next control step + * available on the hardware. + */ +static bool bw_validate(char *buf, unsigned long *data, struct rdt_resource *r) +{ + unsigned long bw, m; + int ret; + + /* + * Only linear delay values is supported for current Intel SKUs. + */ + if (!r->delay_linear) + return false; + + ret = kstrtoul(buf, 10, &bw); + if (ret) + return false; + + if (bw < r->min_bw || bw > r->default_ctrl) + return false; + + m = (bw + r->bw_gran - 1) / r->bw_gran; + *data = m * r->bw_gran; + + return true; +} + +int parse_bw(char *buf, struct rdt_resource *r, struct rdt_domain *d) +{ + unsigned long data; + + if (d->have_new_ctrl) + return -EINVAL; + + if (!bw_validate(buf, &data, r)) + return -EINVAL; + d->new_ctrl = data; + d->have_new_ctrl = true; + + return 0; +} + +/* * Check whether a cache bit mask is valid. The SDM says: * Please note that all (and only) contiguous '1' combinations * are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.). -- 1.9.1