From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:49554 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753793AbdDJOpQ (ORCPT ); Mon, 10 Apr 2017 10:45:16 -0400 Subject: Patch "MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2" has been added to the 4.10-stable tree To: chenhc@lemote.com, Steven.Hill@caviumnetworks.com, gregkh@linuxfoundation.org, john@phrozen.org, ralf@linux-mips.org, wuzhangjin@gmail.com, zhangfx@lemote.com Cc: , From: Date: Mon, 10 Apr 2017 16:44:56 +0200 Message-ID: <1491835496210108@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2 to the 4.10-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: mips-add-mips_cpu_ftlb-for-loongson-3a-r2.patch and it can be found in the queue-4.10 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From 033cffeedbd11c140952b98e8639bf652091a17d Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Thu, 16 Mar 2017 21:00:25 +0800 Subject: MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2 From: Huacai Chen commit 033cffeedbd11c140952b98e8639bf652091a17d upstream. Loongson-3A R2 and newer CPU have FTLB, but Config0.MT is 1, so add MIPS_CPU_FTLB to the CPU options. Signed-off-by: Huacai Chen Cc: John Crispin Cc: Steven J . Hill Cc: Fuxin Zhang Cc: Zhangjin Wu Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15752/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/kernel/cpu-probe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1824,7 +1824,7 @@ static inline void cpu_probe_loongson(st } decode_configs(c); - c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; + c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; c->writecombine = _CACHE_UNCACHED_ACCELERATED; break; default: Patches currently in stable-queue which might be from chenhc@lemote.com are queue-4.10/mips-flush-wrong-invalid-ftlb-entry-for-huge-page.patch queue-4.10/mips-check-tlb-before-handle_ri_rdhwr-for-loongson-3.patch queue-4.10/mips-c-r4k-fix-loongson-3-s-vcache-scache-waysize-calculation.patch queue-4.10/mips-add-mips_cpu_ftlb-for-loongson-3a-r2.patch