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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org, "Richard Henderson" <rth@twiddle.net>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [Qemu-devel] [PATCH v2 4/9] arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
Date: Mon, 10 Apr 2017 18:13:34 +0100	[thread overview]
Message-ID: <1491844419-12485-5-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1491844419-12485-1-git-send-email-peter.maydell@linaro.org>

Move the utility routines gen_set_condexec() and gen_set_pc_im()
up in the file, as we will want to use them from a function
placed earlier in the file than their current location.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/translate.c | 31 +++++++++++++++----------------
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 870e320..a1a0e73 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -893,6 +893,21 @@ static const uint8_t table_logic_cc[16] = {
     1, /* mvn */
 };
 
+static inline void gen_set_condexec(DisasContext *s)
+{
+    if (s->condexec_mask) {
+        uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
+        TCGv_i32 tmp = tcg_temp_new_i32();
+        tcg_gen_movi_i32(tmp, val);
+        store_cpu_field(tmp, condexec_bits);
+    }
+}
+
+static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
+{
+    tcg_gen_movi_i32(cpu_R[15], val);
+}
+
 /* Set PC and Thumb state from an immediate address.  */
 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
 {
@@ -1069,11 +1084,6 @@ DO_GEN_ST(8, MO_UB)
 DO_GEN_ST(16, MO_UW)
 DO_GEN_ST(32, MO_UL)
 
-static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
-{
-    tcg_gen_movi_i32(cpu_R[15], val);
-}
-
 static inline void gen_hvc(DisasContext *s, int imm16)
 {
     /* The pre HVC helper handles cases when HVC gets trapped
@@ -1107,17 +1117,6 @@ static inline void gen_smc(DisasContext *s)
     s->is_jmp = DISAS_SMC;
 }
 
-static inline void
-gen_set_condexec (DisasContext *s)
-{
-    if (s->condexec_mask) {
-        uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_movi_i32(tmp, val);
-        store_cpu_field(tmp, condexec_bits);
-    }
-}
-
 static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
 {
     gen_set_condexec(s);
-- 
2.7.4

  parent reply	other threads:[~2017-04-10 17:34 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-10 17:13 [Qemu-devel] [PATCH v2 0/9] arm: Implement M profile exception return properly Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 1/9] arm: Don't implement BXJ on M-profile CPUs Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 2/9] arm: Thumb shift operations should not permit interworking branches Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 3/9] arm: Factor out "generate right kind of step exception" Peter Maydell
2017-04-10 17:13 ` Peter Maydell [this message]
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 5/9] arm: Move condition-failed codepath generation out of if() Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 6/9] arm: Abstract out "are we singlestepping" test to utility function Peter Maydell
2017-04-10 18:54   ` Philippe Mathieu-Daudé
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 7/9] arm: Track M profile handler mode state in TB flags Peter Maydell
2017-04-17  4:20   ` Philippe Mathieu-Daudé
2017-04-20 14:25     ` Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 8/9] arm: Implement M profile exception return properly Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 9/9] arm: Remove workarounds for old M-profile exception return implementation Peter Maydell
2017-04-15 12:31 ` [Qemu-devel] [PATCH v2 0/9] arm: Implement M profile exception return properly Richard Henderson
2017-04-20 14:28   ` Peter Maydell

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