Re: [PATCH v2] drm/i915: Combine write_domain flushes to a single function

From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915: Combine write_domain flushes to a single function
Date: Wed, 12 Apr 2017 13:06:04 +0300	[thread overview]
Message-ID: <1491991564.3274.19.camel@linux.intel.com> (raw)
In-Reply-To: <20170412094253.5200-1-chris@chris-wilson.co.uk>

On ke, 2017-04-12 at 10:42 +0100, Chris Wilson wrote:
> In the next patch, we will introduce a new cache domain for
> differentiating between GTT access and direct WC access. This will
> require us to include WC in our write_domain flushes. Rather than
> duplicate a third function, combine the existing two into one and
> flushing WC writes will then be automatically handled as well.
> 
> v2: Be smarter and clearer by passing in the write domains to flush (Joonas)
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

<SNIP>

> @@ -266,7 +266,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj,
>  		if (offset >= obj->base.size)
>  			continue;
>  
> -		i915_gem_object_flush_gtt_write_domain(obj);
> +		flush_write_domain(obj, I915_GEM_DOMAIN_CPU);

Forgot the tilde, with that;

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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