From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44030) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tc6-0008Eq-Gq for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:41:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tc5-0004Px-LI for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:41:58 -0400 From: Aaron Lindsay Date: Wed, 19 Apr 2017 13:41:18 -0400 Message-Id: <1492623684-25799-8-git-send-email-alindsay@codeaurora.org> In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> Subject: [Qemu-devel] [PATCH 07/13] target/arm: Implement PMOVSSET List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, mspradli@codeaurora.org, Aaron Lindsay Also modify it to be stored as a uint64_t Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 2 +- target/arm/helper.c | 27 ++++++++++++++++++++++++--- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ae2a294..f3524f6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -310,7 +310,7 @@ typedef struct CPUARMState { uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ uint64_t c9_pmcnten; /* perf monitor counter enables */ - uint32_t c9_pmovsr; /* perf monitor overflow status */ + uint64_t c9_pmovsr; /* perf monitor overflow status */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint64_t c9_pmselr; /* perf monitor counter selection register */ uint64_t c9_pminten; /* perf monitor interrupt enables */ diff --git a/target/arm/helper.c b/target/arm/helper.c index bf9f164..9c01269 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1150,9 +1150,17 @@ static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + value &= PMU_COUNTER_MASK(env); env->cp15.c9_pmovsr &= ~value; } +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &= PMU_COUNTER_MASK(env); + env->cp15.c9_pmovsr |= value; +} + static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1317,10 +1325,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .writefn = pmcntenclr_write }, { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, - .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), - .accessfn = pmreg_access, + .access = PL0_RW, .accessfn = pmreg_access, + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), .writefn = pmovsr_write, - .raw_writefn = raw_write }, + .raw_writefn = raw_write, .resetvalue = 0 }, { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, .access = PL0_RW, .accessfn = pmreg_access, @@ -1328,6 +1336,19 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), .writefn = pmovsr_write, .raw_writefn = raw_write }, + { .name = "PMOVSSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsset_write, + .raw_writefn = raw_write }, + { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsset_write, + .raw_writefn = raw_write }, /* Unimplemented so WI. */ { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP }, -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.