From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Gao Date: Thu, 20 Apr 2017 12:45:49 +0800 Subject: [U-Boot] [PATCH v4 01/11] rockchip: include: grf: Add GRF register declaration for mipi dsi In-Reply-To: <1492663559-8248-1-git-send-email-eric.gao@rock-chips.com> References: <1492663559-8248-1-git-send-email-eric.gao@rock-chips.com> Message-ID: <1492663559-8248-2-git-send-email-eric.gao@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Signed-off-by: Eric Gao --- Changes in v4: None Changes in v3: -Split GRF changes as a single patch Changes in v2: None arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index b340b05..63b3b94 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -440,6 +440,29 @@ enum { GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, GRF_UART_DBG_SEL_C = 2, + /* GRF_SOC_CON20 */ + GRF_DSI0_VOP_SEL_SHIFT = 0, + GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT, + GRF_DSI0_VOP_SEL_B = 0, + GRF_DSI0_VOP_SEL_L, + + /* GRF_SOC_CON22 */ + GRF_DPHY_TX0_RXMODE_SHIFT = 0, + GRF_DPHY_TX0_RXMODE_MASK = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT, + GRF_DPHY_TX0_RXMODE_EN = 0xb, + GRF_DPHY_TX0_RXMODE_DIS = 0, + + GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4, + GRF_DPHY_TX0_TXSTOPMODE_MASK = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT, + GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc, + GRF_DPHY_TX0_TXSTOPMODE_DIS = 0, + + GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12, + GRF_DPHY_TX0_TURNREQUEST_MASK = 0xf000 + << GRF_DPHY_TX0_TURNREQUEST_SHIFT, + GRF_DPHY_TX0_TURNREQUEST_EN = 0x1, + GRF_DPHY_TX0_TURNREQUEST_DIS = 0, + /* PMUGRF_GPIO0A_IOMUX */ PMUGRF_GPIO0A6_SEL_SHIFT = 12, PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, -- 1.9.1