* [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs
@ 2017-04-23 8:43 Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 01/14] cmd: cpu: fix NULL cpu feature prints Álvaro Fernández Rojas
` (13 more replies)
0 siblings, 14 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
This adds support for some of the xDSL Broadcom MIPS SoCs:
- BCM6358
- BCM6328
- BCM63268
However, support for other SoCs could be added in the future:
- Other BCM63xx
- BCM33xx
- BCM71xx
v5: Improve BMIPS CPU driver
v4: Introduce changes suggested by Simon Glass:
- Refactor cmd/cpu.
- Remove device_probe patch for sysreset.
v3: Introduce changes suggested by Simon Glass.
v2: Introduce changes suggested by Daniel Schwierzeck.
Álvaro Fernández Rojas (14):
cmd: cpu: fix NULL cpu feature prints
sysreset: add syscon-reboot driver
MIPS: allow using generic sysreset drivers
serial: add serial driver for BCM6345
cmd: cpu: refactor to ensure devices are probed and improve code style
cpu: add CPU driver for Broadcom MIPS SoCs
ram: add RAM driver for Broadcom MIPS SoCs
MIPS: add initial infrastructure for Broadcom MIPS SoCs
MIPS: add support for Broadcom MIPS BCM6358 SoC family
MIPS: add BMIPS Huawei HG556a board
MIPS: add support for Broadcom MIPS BCM6328 SoC family
MIPS: add BMIPS Comtrend AR-5387un board
MIPS: add support for Broadcom MIPS BCM63268 SoC family
MIPS: add BMIPS Comtrend VR-3032u board
arch/mips/Kconfig | 10 +
arch/mips/Makefile | 1 +
arch/mips/cpu/cpu.c | 2 +
arch/mips/cpu/start.S | 5 +
arch/mips/dts/Makefile | 3 +
arch/mips/dts/brcm,bcm63268.dtsi | 88 +++++++++
arch/mips/dts/brcm,bcm6328.dtsi | 88 +++++++++
arch/mips/dts/brcm,bcm6358.dtsi | 98 ++++++++++
arch/mips/dts/comtrend,ar-5387un.dts | 27 +++
arch/mips/dts/comtrend,vr-3032u.dts | 27 +++
arch/mips/dts/huawei,hg556a.dts | 31 ++++
arch/mips/mach-bmips/Kconfig | 86 +++++++++
arch/mips/mach-bmips/Makefile | 5 +
arch/mips/mach-bmips/dram.c | 37 ++++
arch/mips/mach-bmips/include/ioremap.h | 45 +++++
board/comtrend/ar5387un/Kconfig | 12 ++
board/comtrend/ar5387un/MAINTAINERS | 6 +
board/comtrend/ar5387un/Makefile | 5 +
board/comtrend/ar5387un/ar-5387un.c | 7 +
board/comtrend/vr3032u/Kconfig | 12 ++
board/comtrend/vr3032u/MAINTAINERS | 6 +
board/comtrend/vr3032u/Makefile | 5 +
board/comtrend/vr3032u/vr-3032u.c | 7 +
board/huawei/hg556a/Kconfig | 12 ++
board/huawei/hg556a/MAINTAINERS | 6 +
board/huawei/hg556a/Makefile | 5 +
board/huawei/hg556a/hg556a.c | 7 +
cmd/cpu.c | 31 ++--
configs/comtrend_ar5387un_ram_defconfig | 42 +++++
configs/comtrend_vr3032u_ram_defconfig | 42 +++++
configs/huawei_hg556a_ram_defconfig | 45 +++++
drivers/cpu/Makefile | 2 +
drivers/cpu/bmips_cpu.c | 310 +++++++++++++++++++++++++++++++
drivers/ram/Makefile | 2 +
drivers/ram/bmips_ram.c | 126 +++++++++++++
drivers/serial/Kconfig | 14 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_bcm6345.c | 311 ++++++++++++++++++++++++++++++++
drivers/sysreset/Kconfig | 8 +
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_syscon.c | 76 ++++++++
include/configs/bmips_bcm63268.h | 25 +++
include/configs/bmips_bcm6328.h | 25 +++
include/configs/bmips_bcm6358.h | 30 +++
include/configs/bmips_common.h | 27 +++
include/configs/comtrend_ar5387un.h | 15 ++
include/configs/comtrend_vr3032u.h | 15 ++
include/configs/huawei_hg556a.h | 18 ++
48 files changed, 1792 insertions(+), 17 deletions(-)
create mode 100644 arch/mips/dts/brcm,bcm63268.dtsi
create mode 100644 arch/mips/dts/brcm,bcm6328.dtsi
create mode 100644 arch/mips/dts/brcm,bcm6358.dtsi
create mode 100644 arch/mips/dts/comtrend,ar-5387un.dts
create mode 100644 arch/mips/dts/comtrend,vr-3032u.dts
create mode 100644 arch/mips/dts/huawei,hg556a.dts
create mode 100644 arch/mips/mach-bmips/Kconfig
create mode 100644 arch/mips/mach-bmips/Makefile
create mode 100644 arch/mips/mach-bmips/dram.c
create mode 100644 arch/mips/mach-bmips/include/ioremap.h
create mode 100644 board/comtrend/ar5387un/Kconfig
create mode 100644 board/comtrend/ar5387un/MAINTAINERS
create mode 100644 board/comtrend/ar5387un/Makefile
create mode 100644 board/comtrend/ar5387un/ar-5387un.c
create mode 100644 board/comtrend/vr3032u/Kconfig
create mode 100644 board/comtrend/vr3032u/MAINTAINERS
create mode 100644 board/comtrend/vr3032u/Makefile
create mode 100644 board/comtrend/vr3032u/vr-3032u.c
create mode 100644 board/huawei/hg556a/Kconfig
create mode 100644 board/huawei/hg556a/MAINTAINERS
create mode 100644 board/huawei/hg556a/Makefile
create mode 100644 board/huawei/hg556a/hg556a.c
create mode 100644 configs/comtrend_ar5387un_ram_defconfig
create mode 100644 configs/comtrend_vr3032u_ram_defconfig
create mode 100644 configs/huawei_hg556a_ram_defconfig
create mode 100644 drivers/cpu/bmips_cpu.c
create mode 100644 drivers/ram/bmips_ram.c
create mode 100644 drivers/serial/serial_bcm6345.c
create mode 100644 drivers/sysreset/sysreset_syscon.c
create mode 100644 include/configs/bmips_bcm63268.h
create mode 100644 include/configs/bmips_bcm6328.h
create mode 100644 include/configs/bmips_bcm6358.h
create mode 100644 include/configs/bmips_common.h
create mode 100644 include/configs/comtrend_ar5387un.h
create mode 100644 include/configs/comtrend_vr3032u.h
create mode 100644 include/configs/huawei_hg556a.h
--
2.1.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 01/14] cmd: cpu: fix NULL cpu feature prints
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 02/14] sysreset: add syscon-reboot driver Álvaro Fernández Rojas
` (12 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Commit 740d5d3 added two new features but only one feature name,
which results in NULL prints when device_id feature is selected.
Before:
HG556a # cpu detail
-1: cpu at 0 BCM6358A1
ID = 0, freq = 300 MHz: L1 cache, MMU, NULL
Device ID 0x2a010
-1: cpu at 1 BCM6358A1
ID = 1, freq = 300 MHz: L1 cache, MMU, NULL
Device ID 0x2a010
After:
HG556a # cpu detail
-1: cpu at 0 BCM6358A1
ID = 0, freq = 300 MHz: L1 cache, MMU, Device ID
Device ID 0x2a010
-1: cpu at 1 BCM6358A1
ID = 1, freq = 300 MHz: L1 cache, MMU, Device ID
Device ID 0x2a010
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
v5: No changes.
v4: No changes.
v3: No changes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Add the missing name instead of checking for null names.
cmd/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/cpu.c b/cmd/cpu.c
index bc4dc5c..adfd54a 100644
--- a/cmd/cpu.c
+++ b/cmd/cpu.c
@@ -15,6 +15,7 @@ static const char *cpu_feature_name[CPU_FEAT_COUNT] = {
"L1 cache",
"MMU",
"Microcode",
+ "Device ID",
};
static int print_cpu_list(bool detail)
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 02/14] sysreset: add syscon-reboot driver
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 01/14] cmd: cpu: fix NULL cpu feature prints Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 20:16 ` Daniel Schwierzeck
2017-04-23 8:43 ` [U-Boot] [PATCH v5 03/14] MIPS: allow using generic sysreset drivers Álvaro Fernández Rojas
` (11 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c,
which provides a generic driver for platforms that only require writing a mask
to a regmap offset.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
v5: No chnages.
v4: Rebased.
v3: Introduce changes suggested by Simon Glass:
- Add missing driver description.
- Alphabetically order includes.
- Add priv struct to store regmap during probe.
- Cosmetic fixes.
v2: No changes.
drivers/sysreset/Kconfig | 8 ++++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_syscon.c | 76 ++++++++++++++++++++++++++++++++++++++
3 files changed, 85 insertions(+)
create mode 100644 drivers/sysreset/sysreset_syscon.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 9664630..b2f7464 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -23,4 +23,12 @@ config SYSRESET_PSCI
must be running on your system.
endif
+
+config SYSRESET_SYSCON
+ bool "Enable support for mfd syscon reboot driver"
+ select REGMAP
+ select SYSCON
+ help
+ Reboot support for generic SYSCON mapped register reset.
+
endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 7bb8406..bd352e7 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c
new file mode 100644
index 0000000..adfddb4
--- /dev/null
+++ b/drivers/sysreset/sysreset_syscon.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/power/reset/syscon-reboot.c:
+ * Copyright (C) 2013, Applied Micro Circuits Corporation
+ * Author: Feng Kan <fkan@apm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <regmap.h>
+#include <sysreset.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct syscon_reboot_priv {
+ struct regmap *regmap;
+ unsigned int offset;
+ unsigned int mask;
+};
+
+static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct syscon_reboot_priv *priv = dev_get_priv(dev);
+
+ regmap_write(priv->regmap, priv->offset, priv->mask);
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops syscon_reboot_ops = {
+ .request = syscon_reboot_request,
+};
+
+int syscon_reboot_probe(struct udevice *dev)
+{
+ struct udevice *syscon;
+ struct syscon_reboot_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "regmap", &syscon);
+ if (err) {
+ error("unable to find syscon device\n");
+ return err;
+ }
+
+ priv->regmap = syscon_get_regmap(syscon);
+ if (!priv->regmap) {
+ error("unable to find regmap\n");
+ return -ENODEV;
+ }
+
+ priv->offset = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "offset", 0);
+ priv->mask = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "mask", 0);
+
+ return 0;
+}
+
+static const struct udevice_id syscon_reboot_ids[] = {
+ { .compatible = "syscon-reboot" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(syscon_reboot) = {
+ .name = "syscon_reboot",
+ .id = UCLASS_SYSRESET,
+ .of_match = syscon_reboot_ids,
+ .probe = syscon_reboot_probe,
+ .priv_auto_alloc_size = sizeof(struct syscon_reboot_priv),
+ .ops = &syscon_reboot_ops,
+};
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 03/14] MIPS: allow using generic sysreset drivers
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 01/14] cmd: cpu: fix NULL cpu feature prints Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 02/14] sysreset: add syscon-reboot driver Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 04/14] serial: add serial driver for BCM6345 Álvaro Fernández Rojas
` (10 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Avoid duplicating do_reset definition if SYSRESET is enabled for MIPS
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
v5: No changes.
v4: No changes.
v3: No changes.
v2: No changes.
arch/mips/cpu/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 1b919ed..55e6498 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -12,6 +12,7 @@
#include <asm/mipsregs.h>
#include <asm/reboot.h>
+#ifndef CONFIG_SYSRESET
void __weak _machine_restart(void)
{
fprintf(stderr, "*** reset failed ***\n");
@@ -26,6 +27,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
+#endif
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
{
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 04/14] serial: add serial driver for BCM6345
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (2 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 03/14] MIPS: allow using generic sysreset drivers Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 20:12 ` Daniel Schwierzeck
2017-04-23 8:43 ` [U-Boot] [PATCH v5 05/14] cmd: cpu: refactor to ensure devices are probed and improve code style Álvaro Fernández Rojas
` (9 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
It is based on linux/drivers/tty/serial/bcm63xx_uart.c
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
v5: No changes.
v4: Add more missing register configurations based on CFE.
v3: Several improvements:
- Add missing register configurations based on CFE.
- Replace tabs with whitespaces.
- Cosmetic fixes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Remove unneeded defines.
- Fix incorrect multi-line comment.
drivers/serial/Kconfig | 14 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_bcm6345.c | 311 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 326 insertions(+)
create mode 100644 drivers/serial/serial_bcm6345.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index c0ec2ec..ca776d8 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -134,6 +134,14 @@ config DEBUG_UART_ATMEL
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
+config DEBUG_UART_BCM6345
+ bool "BCM6345 UART"
+ depends on BCM6345_SERIAL
+ help
+ Select this to enable a debug UART on BCM6345 SoCs. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver model serial is running.
+
config DEBUG_UART_NS16550
bool "ns16550"
help
@@ -339,6 +347,12 @@ config ATMEL_USART
configured in the device tree, and input clock frequency can
be got from the clk node.
+config BCM6345_SERIAL
+ bool "Support for BCM6345 UART"
+ depends on DM_SERIAL
+ help
+ Select this to enable UART on BCM6345 SoCs.
+
config FSL_LPUART
bool "Freescale LPUART support"
help
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 4382cf9..dca31b2 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
+obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o
diff --git a/drivers/serial/serial_bcm6345.c b/drivers/serial/serial_bcm6345.c
new file mode 100644
index 0000000..e4d3497
--- /dev/null
+++ b/drivers/serial/serial_bcm6345.c
@@ -0,0 +1,311 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/tty/serial/bcm63xx_uart.c:
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <clk.h>
+#include <debug_uart.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <dm/device.h>
+
+/* UART Control register */
+#define UART_CTL_REG 0x0
+#define UART_CTL_RXTIMEOUT_MASK 0x1f
+#define UART_CTL_RSTRXFIFO_SHIFT 6
+#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
+#define UART_CTL_RSTTXFIFO_SHIFT 7
+#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
+#define UART_CTL_STOPBITS_SHIFT 8
+#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
+#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
+#define UART_CTL_BITSPERSYM_SHIFT 12
+#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
+#define UART_CTL_XMITBRK_SHIFT 14
+#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
+#define UART_CTL_RSVD_SHIFT 15
+#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
+#define UART_CTL_RXPAREVEN_SHIFT 16
+#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
+#define UART_CTL_RXPAREN_SHIFT 17
+#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
+#define UART_CTL_TXPAREVEN_SHIFT 18
+#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
+#define UART_CTL_TXPAREN_SHIFT 19
+#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
+#define UART_CTL_LOOPBACK_SHIFT 20
+#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
+#define UART_CTL_RXEN_SHIFT 21
+#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
+#define UART_CTL_TXEN_SHIFT 22
+#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
+#define UART_CTL_BRGEN_SHIFT 23
+#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
+
+/* UART Baudword register */
+#define UART_BAUD_REG 0x4
+
+/* UART FIFO Config register */
+#define UART_FIFO_CFG_REG 0x8
+#define UART_FIFO_CFG_RX_SHIFT 8
+#define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT)
+#define UART_FIFO_CFG_TX_SHIFT 12
+#define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT)
+
+/* UART Interrupt register */
+#define UART_IR_REG 0x10
+#define UART_IR_STAT(x) (1 << (x))
+#define UART_IR_TXEMPTY 5
+#define UART_IR_RXOVER 7
+#define UART_IR_RXNOTEMPTY 11
+
+/* UART FIFO register */
+#define UART_FIFO_REG 0x14
+#define UART_FIFO_VALID_MASK 0xff
+#define UART_FIFO_FRAMEERR_SHIFT 8
+#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
+#define UART_FIFO_PARERR_SHIFT 9
+#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
+#define UART_FIFO_BRKDET_SHIFT 10
+#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
+#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
+ UART_FIFO_PARERR_MASK | \
+ UART_FIFO_BRKDET_MASK)
+
+struct bcm6345_serial_priv {
+ void __iomem *base;
+ ulong uartclk;
+};
+
+/*
+ * enable rx & tx operation on uart
+ */
+static void bcm6345_serial_enable(void __iomem *base)
+{
+ u32 val;
+
+ val = __raw_readl(base + UART_CTL_REG);
+ val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
+ __raw_writel(val, base + UART_CTL_REG);
+}
+
+/*
+ * disable rx & tx operation on uart
+ */
+static void bcm6345_serial_disable(void __iomem *base)
+{
+ u32 val;
+
+ val = __raw_readl(base + UART_CTL_REG);
+ val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
+ UART_CTL_RXEN_MASK);
+ __raw_writel(val, base + UART_CTL_REG);
+}
+
+/*
+ * clear all unread data in rx fifo and unsent data in tx fifo
+ */
+static void bcm6345_serial_flush(void __iomem *base)
+{
+ u32 val;
+
+ /* empty rx and tx fifo */
+ val = __raw_readl(base + UART_CTL_REG);
+ val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
+ __raw_writel(val, base + UART_CTL_REG);
+
+ /* read any pending char to make sure all irq status are cleared */
+ __raw_readl(base + UART_FIFO_REG);
+}
+
+static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
+{
+ u32 val;
+
+ /* mask all irq and flush port */
+ bcm6345_serial_disable(base);
+ bcm6345_serial_flush(base);
+
+ val = __raw_readl(base + UART_CTL_REG);
+ /* set rx timeout */
+ val &= ~UART_CTL_RXTIMEOUT_MASK;
+ val |= 0x5;
+ /* set stop bits */
+ val &= ~UART_CTL_STOPBITS_MASK;
+ val |= UART_CTL_STOPBITS_1;
+ /* set bits per symbol */
+ val &= ~UART_CTL_BITSPERSYM_MASK;
+ val |= (3 << UART_CTL_BITSPERSYM_SHIFT);
+ /* clear xmit break */
+ val &= ~UART_CTL_XMITBRK_MASK;
+ /* clear reserved bit */
+ val &= ~UART_CTL_RSVD_MASK;
+ /* disable parity */
+ val |= UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK;
+ val &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
+ /* disable loopback */
+ val &= ~UART_CTL_LOOPBACK_MASK;
+ __raw_writel(val, base + UART_CTL_REG);
+
+ val = __raw_readl(base + UART_FIFO_CFG_REG);
+ /* set rx fifo config */
+ val &= ~UART_FIFO_CFG_RX_MASK;
+ val |= (4 << UART_FIFO_CFG_RX_SHIFT);
+ /* set tx fifo config */
+ val &= ~UART_FIFO_CFG_TX_MASK;
+ val |= (4 << UART_FIFO_CFG_TX_SHIFT);
+ __raw_writel(val, base + UART_FIFO_CFG_REG);
+
+ /* set baud rate */
+ val = (clk / baudrate) / 16;
+ if (val & 0x1)
+ val = val;
+ else
+ val = val / 2 - 1;
+ __raw_writel(val, base + UART_BAUD_REG);
+
+ /* clear interrupts */
+ __raw_writel(0, base + UART_IR_REG);
+
+ /* enable uart */
+ bcm6345_serial_enable(base);
+
+ return 0;
+}
+
+static int bcm6345_serial_pending(struct udevice *dev, bool input)
+{
+ struct bcm6345_serial_priv *priv = dev_get_priv(dev);
+ u32 val = __raw_readl(priv->base + UART_IR_REG);
+
+ if (input)
+ return (val & UART_IR_STAT(UART_IR_RXNOTEMPTY)) ? 1 : 0;
+ else
+ return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 0 : 1;
+}
+
+static int bcm6345_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct bcm6345_serial_priv *priv = dev_get_priv(dev);
+
+ return bcm6345_serial_init(priv->base, priv->uartclk, baudrate);
+}
+
+static int bcm6345_serial_putc(struct udevice *dev, const char ch)
+{
+ struct bcm6345_serial_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ val = __raw_readl(priv->base + UART_IR_REG);
+ if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
+ return -EAGAIN;
+
+ __raw_writel(ch, priv->base + UART_FIFO_REG);
+
+ return 0;
+}
+
+static int bcm6345_serial_getc(struct udevice *dev)
+{
+ struct bcm6345_serial_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ val = __raw_readl(priv->base + UART_IR_REG);
+ if (val & UART_IR_STAT(UART_IR_RXOVER)) {
+ /* fifo reset is required to clear interrupt */
+ val = __raw_readl(priv->base + UART_CTL_REG);
+ val |= UART_CTL_RSTRXFIFO_MASK;
+ __raw_writel(val, priv->base + UART_CTL_REG);
+ }
+ if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
+ return -EAGAIN;
+
+ val = __raw_readl(priv->base + UART_FIFO_REG);
+ if (val & UART_FIFO_ANYERR_MASK)
+ return -EAGAIN;
+
+ return (val & UART_FIFO_VALID_MASK);
+}
+
+static int bcm6345_serial_probe(struct udevice *dev)
+{
+ struct bcm6345_serial_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ /* get address */
+ addr = dev_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = ioremap(addr, size);
+
+ /* get clock rate */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+ priv->uartclk = clk_get_rate(&clk) / 2;
+ clk_free(&clk);
+
+ /* initialize serial */
+ return bcm6345_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
+}
+
+static const struct dm_serial_ops bcm6345_serial_ops = {
+ .putc = bcm6345_serial_putc,
+ .pending = bcm6345_serial_pending,
+ .getc = bcm6345_serial_getc,
+ .setbrg = bcm6345_serial_setbrg,
+};
+
+static const struct udevice_id bcm6345_serial_ids[] = {
+ { .compatible = "brcm,bcm6345-uart" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm6345_serial) = {
+ .name = "bcm6345-uart",
+ .id = UCLASS_SERIAL,
+ .of_match = bcm6345_serial_ids,
+ .probe = bcm6345_serial_probe,
+ .priv_auto_alloc_size = sizeof(struct bcm6345_serial_priv),
+ .ops = &bcm6345_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_BCM6345
+static inline void _debug_uart_init(void)
+{
+ void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+
+ bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
+}
+
+static inline void wait_xfered(void __iomem *base)
+{
+ do {
+ u32 val = __raw_readl(base + UART_IR_REG);
+ if (val & UART_IR_STAT(UART_IR_TXEMPTY))
+ break;
+ } while (1);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+
+ wait_xfered(base);
+ __raw_writel(ch, base + UART_FIFO_REG);
+ wait_xfered(base);
+}
+
+DEBUG_UART_FUNCS
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 05/14] cmd: cpu: refactor to ensure devices are probed and improve code style
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (3 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 04/14] serial: add serial driver for BCM6345 Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-24 3:39 ` Simon Glass
2017-04-23 8:43 ` [U-Boot] [PATCH v5 06/14] cpu: add CPU driver for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (8 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Use uclass_first_device and uclass_next_device in order to avoid exceptions
for drivers that aren't probed when cpu ops are requested.
Improve code style and fix indentations.
Fix incorrect line break when cpu info is not available.
Remove unneeded brackets.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
v5: No changes.
v4: Refactor code to use uclass_first_device and uclass_next_device as
requested by Simon Glass.
v3: add new patch to ensure that device is probed.
cmd/cpu.c | 30 +++++++++++++-----------------
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/cmd/cpu.c b/cmd/cpu.c
index adfd54a..6213c72 100644
--- a/cmd/cpu.c
+++ b/cmd/cpu.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -21,20 +22,15 @@ static const char *cpu_feature_name[CPU_FEAT_COUNT] = {
static int print_cpu_list(bool detail)
{
struct udevice *dev;
- struct uclass *uc;
char buf[100];
- int ret;
- ret = uclass_get(UCLASS_CPU, &uc);
- if (ret) {
- printf("Cannot find CPU uclass\n");
- return ret;
- }
- uclass_foreach_dev(dev, uc) {
+ for (uclass_first_device(UCLASS_CPU, &dev);
+ dev;
+ uclass_next_device(&dev)) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
struct cpu_info info;
- bool first;
- int i;
+ bool first = true;
+ int ret, i;
ret = cpu_get_desc(dev, buf, sizeof(buf));
printf("%3d: %-10s %s\n", dev->seq, dev->name,
@@ -45,13 +41,12 @@ static int print_cpu_list(bool detail)
if (ret) {
printf("\t(no detail available");
if (ret != -ENOSYS)
- printf(": err=%d\n", ret);
+ printf(": err=%d", ret);
printf(")\n");
continue;
}
printf("\tID = %d, freq = ", plat->cpu_id);
print_freq(info.cpu_freq, "");
- first = true;
for (i = 0; i < CPU_FEAT_COUNT; i++) {
if (info.features & (1 << i)) {
printf("%s%s", first ? ": " : ", ",
@@ -60,10 +55,9 @@ static int print_cpu_list(bool detail)
}
}
printf("\n");
- if (info.features & (1 << CPU_FEAT_UCODE)) {
+ if (info.features & (1 << CPU_FEAT_UCODE))
printf("\tMicrocode version %#x\n",
plat->ucode_version);
- }
if (info.features & (1 << CPU_FEAT_DEVICE_ID))
printf("\tDevice ID %#lx\n", plat->device_id);
}
@@ -71,7 +65,8 @@ static int print_cpu_list(bool detail)
return 0;
}
-static int do_cpu_list(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_cpu_list(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
{
if (print_cpu_list(false))
return CMD_RET_FAILURE;
@@ -97,7 +92,7 @@ static cmd_tbl_t cmd_cpu_sub[] = {
* Process a cpu sub-command
*/
static int do_cpu(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+ char * const argv[])
{
cmd_tbl_t *c = NULL;
@@ -106,7 +101,8 @@ static int do_cpu(cmd_tbl_t *cmdtp, int flag, int argc,
argv++;
if (argc)
- c = find_cmd_tbl(argv[0], cmd_cpu_sub, ARRAY_SIZE(cmd_cpu_sub));
+ c = find_cmd_tbl(argv[0], cmd_cpu_sub,
+ ARRAY_SIZE(cmd_cpu_sub));
if (c)
return c->cmd(cmdtp, flag, argc, argv);
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 06/14] cpu: add CPU driver for Broadcom MIPS SoCs
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (4 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 05/14] cmd: cpu: refactor to ensure devices are probed and improve code style Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-24 3:39 ` Simon Glass
2017-04-23 8:43 ` [U-Boot] [PATCH v5 07/14] ram: add RAM " Álvaro Fernández Rojas
` (7 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
v5: Add specific desc functions.
v4: No changes.
v3: Several improvements:
- Probe driver correctly.
- Allocate size for priv struct.
- Cosmetic fixes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Get register base from DT.
drivers/cpu/Makefile | 2 +
drivers/cpu/bmips_cpu.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 312 insertions(+)
create mode 100644 drivers/cpu/bmips_cpu.c
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index 8710160..db515f6 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -5,3 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_CPU) += cpu-uclass.o
+
+obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
new file mode 100644
index 0000000..b46262b
--- /dev/null
+++ b/drivers/cpu/bmips_cpu.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/cpu.c:
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REV_CHIPID_SHIFT 16
+#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
+#define REV_LONG_CHIPID_SHIFT 12
+#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
+#define REV_REVID_SHIFT 0
+#define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
+
+#define REG_BCM6328_OTP 0x62c
+#define BCM6328_TP1_DISABLED BIT(9)
+
+#define REG_BCM6328_MISC_STRAPBUS 0x1a40
+#define STRAPBUS_6328_FCVO_SHIFT 7
+#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
+
+#define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8
+#define DMIPSPLLCFG_6358_M1_SHIFT 0
+#define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
+#define DMIPSPLLCFG_6358_N1_SHIFT 23
+#define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
+#define DMIPSPLLCFG_6358_N2_SHIFT 29
+#define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
+
+#define REG_BCM63268_MISC_STRAPBUS 0x1814
+#define STRAPBUS_63268_FCVO_SHIFT 21
+#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
+
+struct bmips_cpu_priv;
+
+struct bmips_cpu_hw {
+ int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
+ ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
+ int (*get_cpu_count)(struct bmips_cpu_priv *);
+};
+
+struct bmips_cpu_priv {
+ void __iomem *regs;
+ const struct bmips_cpu_hw *hw;
+};
+
+/* Specific CPU Ops */
+static int bcm6358_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
+ int size)
+{
+ unsigned short cpu_id;
+ unsigned char cpu_rev;
+ u32 val;
+
+ val = __raw_readl(priv->regs);
+ cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
+ cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
+
+ snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
+
+ return 0;
+}
+
+static int bcm6328_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
+ int size)
+{
+ unsigned int cpu_id;
+ unsigned char cpu_rev;
+ u32 val;
+
+ val = __raw_readl(priv->regs);
+ cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
+ cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
+
+ snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
+
+ return 0;
+}
+
+static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+ unsigned int mips_pll_fcvo;
+
+ mips_pll_fcvo = __raw_readl(priv->regs + REG_BCM6328_MISC_STRAPBUS);
+ mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
+ >> STRAPBUS_6328_FCVO_SHIFT;
+
+ switch (mips_pll_fcvo) {
+ case 0x12:
+ case 0x14:
+ case 0x19:
+ return 160000000;
+ case 0x1c:
+ return 192000000;
+ case 0x13:
+ case 0x15:
+ return 200000000;
+ case 0x1a:
+ return 384000000;
+ case 0x16:
+ return 400000000;
+ default:
+ return 320000000;
+ }
+}
+
+static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+ unsigned int tmp, n1, n2, m1;
+
+ tmp = __raw_readl(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
+ n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
+ n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
+ m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
+
+ return (16 * 1000000 * n1 * n2) / m1;
+}
+
+static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+ unsigned int mips_pll_fcvo;
+
+ mips_pll_fcvo = __raw_readl(priv->regs + REG_BCM63268_MISC_STRAPBUS);
+ mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
+ >> STRAPBUS_63268_FCVO_SHIFT;
+
+ switch (mips_pll_fcvo) {
+ case 0x3:
+ case 0xe:
+ return 320000000;
+ case 0xa:
+ return 333000000;
+ case 0x2:
+ case 0xb:
+ case 0xf:
+ return 400000000;
+ default:
+ return 0;
+ }
+}
+
+static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
+{
+ u32 val = __raw_readl(priv->regs + REG_BCM6328_OTP);
+
+ if (val & BCM6328_TP1_DISABLED)
+ return 1;
+ else
+ return 2;
+}
+
+static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
+{
+ return 2;
+}
+
+static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
+ .get_cpu_desc = bcm6328_get_cpu_desc,
+ .get_cpu_freq = bcm6328_get_cpu_freq,
+ .get_cpu_count = bcm6328_get_cpu_count,
+};
+
+static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
+ .get_cpu_desc = bcm6358_get_cpu_desc,
+ .get_cpu_freq = bcm6358_get_cpu_freq,
+ .get_cpu_count = bcm6358_get_cpu_count,
+};
+
+static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
+ .get_cpu_desc = bcm6328_get_cpu_desc,
+ .get_cpu_freq = bcm63268_get_cpu_freq,
+ .get_cpu_count = bcm6358_get_cpu_count,
+};
+
+/* Generic CPU Ops */
+static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
+{
+ struct bmips_cpu_priv *priv = dev_get_priv(dev);
+ const struct bmips_cpu_hw *hw = priv->hw;
+
+ return hw->get_cpu_desc(priv, buf, size);
+}
+
+static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ struct bmips_cpu_priv *priv = dev_get_priv(dev);
+ const struct bmips_cpu_hw *hw = priv->hw;
+
+ info->cpu_freq = hw->get_cpu_freq(priv);
+ info->features = BIT(CPU_FEAT_L1_CACHE);
+ info->features |= BIT(CPU_FEAT_MMU);
+ info->features |= BIT(CPU_FEAT_DEVICE_ID);
+
+ return 0;
+}
+
+static int bmips_cpu_get_count(struct udevice *dev)
+{
+ struct bmips_cpu_priv *priv = dev_get_priv(dev);
+ const struct bmips_cpu_hw *hw = priv->hw;
+
+ return hw->get_cpu_count(priv);
+}
+
+static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size)
+{
+ snprintf(buf, size, "Broadcom");
+
+ return 0;
+}
+
+static const struct cpu_ops bmips_cpu_ops = {
+ .get_desc = bmips_cpu_get_desc,
+ .get_info = bmips_cpu_get_info,
+ .get_count = bmips_cpu_get_count,
+ .get_vendor = bmips_cpu_get_vendor,
+};
+
+/* BMIPS CPU driver */
+int bmips_cpu_bind(struct udevice *dev)
+{
+ struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+ plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "reg", -1);
+ plat->device_id = read_c0_prid();
+
+ return 0;
+}
+
+int bmips_cpu_probe(struct udevice *dev)
+{
+ struct bmips_cpu_priv *priv = dev_get_priv(dev);
+ const struct bmips_cpu_hw *hw =
+ (const struct bmips_cpu_hw *)dev_get_driver_data(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = dev_get_addr_size_index(dev_get_parent(dev), 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+ priv->hw = hw;
+
+ return 0;
+}
+
+static const struct udevice_id bmips_cpu_ids[] = {
+ {
+ .compatible = "brcm,bcm6328-cpu",
+ .data = (ulong)&bmips_cpu_bcm6328,
+ }, {
+ .compatible = "brcm,bcm6358-cpu",
+ .data = (ulong)&bmips_cpu_bcm6358,
+ }, {
+ .compatible = "brcm,bcm63268-cpu",
+ .data = (ulong)&bmips_cpu_bcm63268,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bmips_cpu_drv) = {
+ .name = "bmips_cpu",
+ .id = UCLASS_CPU,
+ .of_match = bmips_cpu_ids,
+ .bind = bmips_cpu_bind,
+ .probe = bmips_cpu_probe,
+ .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
+ .ops = &bmips_cpu_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ struct cpu_info cpu;
+ struct udevice *dev;
+ int err;
+ char desc[100];
+
+ err = uclass_get_device(UCLASS_CPU, 0, &dev);
+ if (err)
+ return 0;
+
+ err = cpu_get_info(dev, &cpu);
+ if (err)
+ return 0;
+
+ err = cpu_get_desc(dev, desc, sizeof(desc));
+ if (err)
+ return 0;
+
+ printf("Chip ID: %s, MIPS: ", desc);
+ print_freq(cpu.cpu_freq, "\n");
+
+ return 0;
+}
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 07/14] ram: add RAM driver for Broadcom MIPS SoCs
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (5 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 06/14] cpu: add CPU driver for Broadcom MIPS SoCs Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 08/14] MIPS: add initial infrastructure " Álvaro Fernández Rojas
` (6 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
v5: No changes.
v4: No changes.
v3: Rename of_match to ids.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
drivers/ram/Makefile | 2 +
drivers/ram/bmips_ram.c | 126 ++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 128 insertions(+)
create mode 100644 drivers/ram/bmips_ram.c
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 0e10249..818dd9f 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -6,3 +6,5 @@
#
obj-$(CONFIG_RAM) += ram-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_ram.o
+
+obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c
new file mode 100644
index 0000000..28aff0c
--- /dev/null
+++ b/drivers/ram/bmips_ram.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/cpu.c:
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+#define MEMC_CFG_REG 0x4
+#define MEMC_CFG_32B_SHIFT 1
+#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
+#define MEMC_CFG_COL_SHIFT 3
+#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
+#define MEMC_CFG_ROW_SHIFT 6
+#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
+
+#define DDR_CSEND_REG 0x8
+
+struct bmips_ram_priv;
+
+struct bmips_ram_hw {
+ ulong (*get_ram_size)(struct bmips_ram_priv *);
+};
+
+struct bmips_ram_priv {
+ void __iomem *regs;
+ const struct bmips_ram_hw *hw;
+};
+
+static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
+{
+ return __raw_readl(priv->regs + DDR_CSEND_REG) << 24;
+}
+
+static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
+{
+ unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+ u32 val;
+
+ val = __raw_readl(priv->regs + MEMC_CFG_REG);
+ rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
+ cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
+ is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
+ banks = 2;
+
+ /* 0 => 11 address bits ... 2 => 13 address bits */
+ rows += 11;
+
+ /* 0 => 8 address bits ... 2 => 10 address bits */
+ cols += 8;
+
+ return 1 << (cols + rows + (is_32bits + 1) + banks);
+}
+
+static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct bmips_ram_priv *priv = dev_get_priv(dev);
+ const struct bmips_ram_hw *hw = priv->hw;
+
+ info->base = 0x80000000;
+ info->size = hw->get_ram_size(priv);
+
+ return 0;
+}
+
+static const struct ram_ops bmips_ram_ops = {
+ .get_info = bmips_ram_get_info,
+};
+
+static const struct bmips_ram_hw bmips_ram_bcm6328 = {
+ .get_ram_size = bcm6328_get_ram_size,
+};
+
+static const struct bmips_ram_hw bmips_ram_bcm6358 = {
+ .get_ram_size = bcm6358_get_ram_size,
+};
+
+static const struct udevice_id bmips_ram_ids[] = {
+ {
+ .compatible = "brcm,bcm6328-mc",
+ .data = (ulong)&bmips_ram_bcm6328,
+ }, {
+ .compatible = "brcm,bcm6358-mc",
+ .data = (ulong)&bmips_ram_bcm6358,
+ }, {
+ .compatible = "brcm,bcm63268-mc",
+ .data = (ulong)&bmips_ram_bcm6328,
+ },
+ { /* sentinel */ }
+};
+
+static int bmips_ram_probe(struct udevice *dev)
+{
+ struct bmips_ram_priv *priv = dev_get_priv(dev);
+ const struct bmips_ram_hw *hw =
+ (const struct bmips_ram_hw *)dev_get_driver_data(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = dev_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+ priv->hw = hw;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bmips_ram) = {
+ .name = "bmips-mc",
+ .id = UCLASS_RAM,
+ .of_match = bmips_ram_ids,
+ .probe = bmips_ram_probe,
+ .priv_auto_alloc_size = sizeof(struct bmips_ram_priv),
+ .ops = &bmips_ram_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 08/14] MIPS: add initial infrastructure for Broadcom MIPS SoCs
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (6 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 07/14] ram: add RAM " Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 20:23 ` Daniel Schwierzeck
2017-04-23 8:43 ` [U-Boot] [PATCH v5 09/14] MIPS: add support for Broadcom MIPS BCM6358 SoC family Álvaro Fernández Rojas
` (5 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
v4: No changes.
v5: No changes.
v3: Select CONFIG_REMAKE_ELF.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Replace initdram with dram_init.
- Merge with "fix first CPU check" patch.
arch/mips/Kconfig | 10 ++++++++++
arch/mips/Makefile | 1 +
arch/mips/cpu/start.S | 5 +++++
arch/mips/mach-bmips/Kconfig | 22 ++++++++++++++++++++++
arch/mips/mach-bmips/Makefile | 5 +++++
arch/mips/mach-bmips/dram.c | 37 +++++++++++++++++++++++++++++++++++++
include/configs/bmips_common.h | 27 +++++++++++++++++++++++++++
7 files changed, 107 insertions(+)
create mode 100644 arch/mips/mach-bmips/Kconfig
create mode 100644 arch/mips/mach-bmips/Makefile
create mode 100644 arch/mips/mach-bmips/dram.c
create mode 100644 include/configs/bmips_common.h
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d97930e..c97ea41 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -75,6 +75,15 @@ config ARCH_ATH79
select OF_CONTROL
select DM
+config ARCH_BMIPS
+ bool "Support BMIPS SoCs"
+ select OF_CONTROL
+ select DM
+ select CLK
+ select CPU
+ select RAM
+ select SYSRESET
+
config MACH_PIC32
bool "Support Microchip PIC32"
select OF_CONTROL
@@ -123,6 +132,7 @@ source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-bmips/Kconfig"
source "arch/mips/mach-pic32/Kconfig"
if MIPS
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index efe7e44..c30d4ef 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -15,6 +15,7 @@ libs-y += arch/mips/lib/
machine-$(CONFIG_SOC_AU1X00) += au1x00
machine-$(CONFIG_ARCH_ATH79) += ath79
+machine-$(CONFIG_ARCH_BMIPS) += bmips
machine-$(CONFIG_MACH_PIC32) += pic32
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index f7dee81..5c1ad00 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -151,8 +151,13 @@ reset:
mfc0 t0, CP0_GLOBALNUMBER
#endif
+#ifdef CONFIG_ARCH_BMIPS
+1: mfc0 t0, CP0_DIAGNOSTIC, 3
+ and t0, t0, (1 << 31)
+#else
1: mfc0 t0, CP0_EBASE
and t0, t0, EBASE_CPUNUM
+#endif
/* Hang if this isn't the first CPU in the system */
2: beqz t0, 4f
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
new file mode 100644
index 0000000..42a7e41
--- /dev/null
+++ b/arch/mips/mach-bmips/Kconfig
@@ -0,0 +1,22 @@
+menu "Broadcom MIPS platforms"
+ depends on ARCH_BMIPS
+
+config SYS_SOC
+ default "none"
+
+choice
+ prompt "Boot mode"
+
+config BMIPS_BOOT_RAM
+ bool "RAM boot"
+ depends on BMIPS_SUPPORTS_BOOT_RAM
+ help
+ This builds an image that is linked to a RAM address. Caches are
+ disabled and environment is built in.
+
+endchoice
+
+config BMIPS_SUPPORTS_BOOT_RAM
+ bool
+
+endmenu
diff --git a/arch/mips/mach-bmips/Makefile b/arch/mips/mach-bmips/Makefile
new file mode 100644
index 0000000..f432acc
--- /dev/null
+++ b/arch/mips/mach-bmips/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += dram.o
diff --git a/arch/mips/mach-bmips/dram.c b/arch/mips/mach-bmips/dram.c
new file mode 100644
index 0000000..b19b28a
--- /dev/null
+++ b/arch/mips/mach-bmips/dram.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2016 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ram.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int err;
+
+ err = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (err) {
+ debug("DRAM init failed: %d\n", err);
+ return 0;
+ }
+
+ err = ram_get_info(dev, &ram);
+ if (err) {
+ debug("Cannot get DRAM size: %d\n", err);
+ return 0;
+ }
+
+ debug("SDRAM base=%zx, size=%x\n", ram.base, ram.size);
+
+ gd->ram_size = ram.size;
+
+ return 0;
+}
diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h
new file mode 100644
index 0000000..3d67729
--- /dev/null
+++ b/include/configs/bmips_common.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_COMMON_H
+#define __CONFIG_BMIPS_COMMON_H
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START 0xa0000000
+#define CONFIG_SYS_MEMTEST_END 0xa2000000
+
+/* Serial */
+#define CONFIG_BAUDRATE 115200
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS 24
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#define CONFIG_SYS_CBSIZE 512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_REMAKE_ELF
+
+#endif /* __CONFIG_BMIPS_COMMON_H */
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 09/14] MIPS: add support for Broadcom MIPS BCM6358 SoC family
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (7 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 08/14] MIPS: add initial infrastructure " Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 10/14] MIPS: add BMIPS Huawei HG556a board Álvaro Fernández Rojas
` (4 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
v5: No changes.
v4: No changes.
v3: Add cfi-flash defines.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Add PERF_BASE to cpus.
- Merge with "fix ioremap for BCM6358" patch.
- Add a custom ioremap.h instead of modifying the generic one.
arch/mips/dts/brcm,bcm6358.dtsi | 98 ++++++++++++++++++++++++++++++++++
arch/mips/mach-bmips/Kconfig | 18 ++++++-
arch/mips/mach-bmips/include/ioremap.h | 45 ++++++++++++++++
include/configs/bmips_bcm6358.h | 30 +++++++++++
4 files changed, 190 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/dts/brcm,bcm6358.dtsi
create mode 100644 arch/mips/mach-bmips/include/ioremap.h
create mode 100644 include/configs/bmips_bcm6358.h
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi
new file mode 100644
index 0000000..c7ba7e0
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6358.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6358";
+
+ cpus {
+ reg = <0xfffe0000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu at 0 {
+ compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu at 1 {
+ compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ pflash: nor at 1e000000 {
+ compatible = "cfi-flash";
+ reg = <0x1e000000 0x2000000>;
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_cntl: syscon at fffe0000 {
+ compatible = "syscon";
+ reg = <0xfffe0000 0xc>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&periph_cntl>;
+ offset = <0x8>;
+ mask = <0x1>;
+ };
+
+ uart0: serial at fffe0100 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0xfffe0100 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ uart1: serial at fffe0120 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0xfffe0120 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ memory-controller at fffe1200 {
+ compatible = "brcm,bcm6358-mc";
+ reg = <0xfffe1200 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 42a7e41..efdb827 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -2,7 +2,23 @@ menu "Broadcom MIPS platforms"
depends on ARCH_BMIPS
config SYS_SOC
- default "none"
+ default "bcm6358" if SOC_BMIPS_BCM6358
+
+choice
+ prompt "Broadcom MIPS SoC select"
+
+config SOC_BMIPS_BCM6358
+ bool "BMIPS BCM6358 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
+
+endchoice
choice
prompt "Boot mode"
diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h
new file mode 100644
index 0000000..404690e
--- /dev/null
+++ b/arch/mips/mach-bmips/include/ioremap.h
@@ -0,0 +1,45 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_MACH_BMIPS_IOREMAP_H
+#define __ASM_MACH_BMIPS_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+ phys_addr_t size)
+{
+ return phys_addr;
+}
+
+static inline int is_bmips_internal_registers(phys_addr_t offset)
+{
+#if defined(CONFIG_SOC_BMIPS_BCM6358)
+ if (offset >= 0xfffe0000)
+ return 1;
+#endif
+
+ return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
+{
+ if (is_bmips_internal_registers(offset))
+ return (void __iomem *)offset;
+
+ return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+ return is_bmips_internal_registers((unsigned long)addr);
+}
+
+#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_BMIPS_IOREMAP_H */
diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h
new file mode 100644
index 0000000..a7af1ca
--- /dev/null
+++ b/include/configs/bmips_bcm6358.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6358_H
+#define __CONFIG_BMIPS_BCM6358_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 150000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SYS_FLASH_BASE 0xbe000000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+
+#endif /* __CONFIG_BMIPS_BCM6358_H */
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 10/14] MIPS: add BMIPS Huawei HG556a board
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (8 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 09/14] MIPS: add support for Broadcom MIPS BCM6358 SoC family Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 11/14] MIPS: add support for Broadcom MIPS BCM6328 SoC family Álvaro Fernández Rojas
` (3 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
v5: No changes.
v4: No changes.
v3: Add cfi-flash support.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Remove DEBUG_UART from defconfig.
arch/mips/dts/Makefile | 1 +
arch/mips/dts/huawei,hg556a.dts | 31 +++++++++++++++++++++++++
arch/mips/mach-bmips/Kconfig | 12 ++++++++++
board/huawei/hg556a/Kconfig | 12 ++++++++++
board/huawei/hg556a/MAINTAINERS | 6 +++++
board/huawei/hg556a/Makefile | 5 +++++
board/huawei/hg556a/hg556a.c | 7 ++++++
configs/huawei_hg556a_ram_defconfig | 45 +++++++++++++++++++++++++++++++++++++
include/configs/huawei_hg556a.h | 18 +++++++++++++++
9 files changed, 137 insertions(+)
create mode 100644 arch/mips/dts/huawei,hg556a.dts
create mode 100644 board/huawei/hg556a/Kconfig
create mode 100644 board/huawei/hg556a/MAINTAINERS
create mode 100644 board/huawei/hg556a/Makefile
create mode 100644 board/huawei/hg556a/hg556a.c
create mode 100644 configs/huawei_hg556a_ram_defconfig
create mode 100644 include/configs/huawei_hg556a.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 30fcc2b..1843b77 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
+dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts
new file mode 100644
index 0000000..08ef2c1
--- /dev/null
+++ b/arch/mips/dts/huawei,hg556a.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6358.dtsi"
+
+/ {
+ model = "Huawei HG556a Board";
+ compatible = "huawei,hg556a", "brcm,bcm6358";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&pflash {
+ status = "okay";
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index efdb827..2867ad8 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -21,6 +21,16 @@ config SOC_BMIPS_BCM6358
endchoice
choice
+ prompt "Board select"
+
+config BOARD_HUAWEI_HG556A
+ bool "Huawei HG556a board"
+ depends on SOC_BMIPS_BCM6358
+ select BMIPS_SUPPORTS_BOOT_RAM
+
+endchoice
+
+choice
prompt "Boot mode"
config BMIPS_BOOT_RAM
@@ -35,4 +45,6 @@ endchoice
config BMIPS_SUPPORTS_BOOT_RAM
bool
+source "board/huawei/hg556a/Kconfig"
+
endmenu
diff --git a/board/huawei/hg556a/Kconfig b/board/huawei/hg556a/Kconfig
new file mode 100644
index 0000000..88622d0
--- /dev/null
+++ b/board/huawei/hg556a/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_HUAWEI_HG556A
+
+config SYS_BOARD
+ default "hg556a"
+
+config SYS_VENDOR
+ default "huawei"
+
+config SYS_CONFIG_NAME
+ default "huawei_hg556a"
+
+endif
diff --git a/board/huawei/hg556a/MAINTAINERS b/board/huawei/hg556a/MAINTAINERS
new file mode 100644
index 0000000..3ead7e4
--- /dev/null
+++ b/board/huawei/hg556a/MAINTAINERS
@@ -0,0 +1,6 @@
+HUAWEI HG556A BOARD
+M: Álvaro Fernández Rojas <noltari@gmail.com>
+S: Maintained
+F: board/huawei/hg556a/
+F: include/configs/huawei_hg556a.h
+F: configs/huawei_hg556a_ram_defconfig
diff --git a/board/huawei/hg556a/Makefile b/board/huawei/hg556a/Makefile
new file mode 100644
index 0000000..ace0ed3
--- /dev/null
+++ b/board/huawei/hg556a/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += hg556a.o
diff --git a/board/huawei/hg556a/hg556a.c b/board/huawei/hg556a/hg556a.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/huawei/hg556a/hg556a.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig
new file mode 100644
index 0000000..ca8507e
--- /dev/null
+++ b/configs/huawei_hg556a_ram_defconfig
@@ -0,0 +1,45 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BOARD_HUAWEI_HG556A=y
+CONFIG_CFI_FLASH=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_FLASH=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a"
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SOC_BMIPS_BCM6358=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_PROMPT="HG556a # "
+CONFIG_SYS_TEXT_BASE=0x80010000
diff --git a/include/configs/huawei_hg556a.h b/include/configs/huawei_hg556a.h
new file mode 100644
index 0000000..6d5300e
--- /dev/null
+++ b/include/configs/huawei_hg556a.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6358.h>
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 11/14] MIPS: add support for Broadcom MIPS BCM6328 SoC family
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (9 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 10/14] MIPS: add BMIPS Huawei HG556a board Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 12/14] MIPS: add BMIPS Comtrend AR-5387un board Álvaro Fernández Rojas
` (2 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
v5: No changes.
v4: No changes.
v3: No changes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Add PERF_BASE to cpus.
arch/mips/dts/brcm,bcm6328.dtsi | 88 +++++++++++++++++++++++++++++++++++++++++
arch/mips/mach-bmips/Kconfig | 12 ++++++
include/configs/bmips_bcm6328.h | 25 ++++++++++++
3 files changed, 125 insertions(+)
create mode 100644 arch/mips/dts/brcm,bcm6328.dtsi
create mode 100644 include/configs/bmips_bcm6328.h
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
new file mode 100644
index 0000000..707e755
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6328";
+
+ cpus {
+ reg = <0x10000000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu at 0 {
+ compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu at 1 {
+ compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ reset_cntl: syscon at 10000068 {
+ compatible = "syscon";
+ reg = <0x10000068 0x4>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&reset_cntl>;
+ offset = <0>;
+ mask = <0x1>;
+ };
+
+ uart0: serial at 10000100 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x10000100 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ uart1: serial at 10000120 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x10000120 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ memory-controller at 10003000 {
+ compatible = "brcm,bcm6328-mc";
+ reg = <0x10003000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 2867ad8..4c74cee 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -2,11 +2,23 @@ menu "Broadcom MIPS platforms"
depends on ARCH_BMIPS
config SYS_SOC
+ default "bcm6328" if SOC_BMIPS_BCM6328
default "bcm6358" if SOC_BMIPS_BCM6358
choice
prompt "Broadcom MIPS SoC select"
+config SOC_BMIPS_BCM6328
+ bool "BMIPS BCM6328 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
+
config SOC_BMIPS_BCM6358
bool "BMIPS BCM6358 family"
select SUPPORTS_BIG_ENDIAN
diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
new file mode 100644
index 0000000..a5c9a2e
--- /dev/null
+++ b/include/configs/bmips_bcm6328.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6328_H
+#define __CONFIG_BMIPS_BCM6328_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6328_H */
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 12/14] MIPS: add BMIPS Comtrend AR-5387un board
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (10 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 11/14] MIPS: add support for Broadcom MIPS BCM6328 SoC family Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 13/14] MIPS: add support for Broadcom MIPS BCM63268 SoC family Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 14/14] MIPS: add BMIPS Comtrend VR-3032u board Álvaro Fernández Rojas
13 siblings, 0 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
v5: No changes.
v4: No changes.
v3: No changes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Remove DEBUG_UART from defconfig.
arch/mips/dts/Makefile | 1 +
arch/mips/dts/comtrend,ar-5387un.dts | 27 +++++++++++++++++++++
arch/mips/mach-bmips/Kconfig | 6 +++++
board/comtrend/ar5387un/Kconfig | 12 ++++++++++
board/comtrend/ar5387un/MAINTAINERS | 6 +++++
board/comtrend/ar5387un/Makefile | 5 ++++
board/comtrend/ar5387un/ar-5387un.c | 7 ++++++
configs/comtrend_ar5387un_ram_defconfig | 42 +++++++++++++++++++++++++++++++++
include/configs/comtrend_ar5387un.h | 15 ++++++++++++
9 files changed, 121 insertions(+)
create mode 100644 arch/mips/dts/comtrend,ar-5387un.dts
create mode 100644 board/comtrend/ar5387un/Kconfig
create mode 100644 board/comtrend/ar5387un/MAINTAINERS
create mode 100644 board/comtrend/ar5387un/Makefile
create mode 100644 board/comtrend/ar5387un/ar-5387un.c
create mode 100644 configs/comtrend_ar5387un_ram_defconfig
create mode 100644 include/configs/comtrend_ar5387un.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 1843b77..0805819 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
+dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts
new file mode 100644
index 0000000..f9c4a1c
--- /dev/null
+++ b/arch/mips/dts/comtrend,ar-5387un.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6328.dtsi"
+
+/ {
+ model = "Comtrend AR-5387un Board";
+ compatible = "comtrend,ar5387-un", "brcm,bcm6328";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 4c74cee..ffb6ddd 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -35,6 +35,11 @@ endchoice
choice
prompt "Board select"
+config BOARD_COMTREND_AR5387UN
+ bool "Comtrend AR-5387un board"
+ depends on SOC_BMIPS_BCM6328
+ select BMIPS_SUPPORTS_BOOT_RAM
+
config BOARD_HUAWEI_HG556A
bool "Huawei HG556a board"
depends on SOC_BMIPS_BCM6358
@@ -57,6 +62,7 @@ endchoice
config BMIPS_SUPPORTS_BOOT_RAM
bool
+source "board/comtrend/ar5387un/Kconfig"
source "board/huawei/hg556a/Kconfig"
endmenu
diff --git a/board/comtrend/ar5387un/Kconfig b/board/comtrend/ar5387un/Kconfig
new file mode 100644
index 0000000..45ab7e2
--- /dev/null
+++ b/board/comtrend/ar5387un/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_AR5387UN
+
+config SYS_BOARD
+ default "ar5387un"
+
+config SYS_VENDOR
+ default "comtrend"
+
+config SYS_CONFIG_NAME
+ default "comtrend_ar5387un"
+
+endif
diff --git a/board/comtrend/ar5387un/MAINTAINERS b/board/comtrend/ar5387un/MAINTAINERS
new file mode 100644
index 0000000..bcaac64
--- /dev/null
+++ b/board/comtrend/ar5387un/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND AR-5387UN BOARD
+M: Álvaro Fernández Rojas <noltari@gmail.com>
+S: Maintained
+F: board/comtrend/ar-5387un/
+F: include/configs/comtrend_ar5387un.h
+F: configs/comtrend_ar5387un_ram_defconfig
diff --git a/board/comtrend/ar5387un/Makefile b/board/comtrend/ar5387un/Makefile
new file mode 100644
index 0000000..9de1cd2
--- /dev/null
+++ b/board/comtrend/ar5387un/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ar-5387un.o
diff --git a/board/comtrend/ar5387un/ar-5387un.c b/board/comtrend/ar5387un/ar-5387un.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/comtrend/ar5387un/ar-5387un.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig
new file mode 100644
index 0000000..004fd16
--- /dev/null
+++ b/configs/comtrend_ar5387un_ram_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BOARD_COMTREND_AR5387UN=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un"
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SOC_BMIPS_BCM6328=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_NO_FLASH=y
+CONFIG_SYS_PROMPT="AR-5387un # "
+CONFIG_SYS_TEXT_BASE=0x80010000
diff --git a/include/configs/comtrend_ar5387un.h b/include/configs/comtrend_ar5387un.h
new file mode 100644
index 0000000..8803506
--- /dev/null
+++ b/include/configs/comtrend_ar5387un.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6328.h>
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 13/14] MIPS: add support for Broadcom MIPS BCM63268 SoC family
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (11 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 12/14] MIPS: add BMIPS Comtrend AR-5387un board Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 14/14] MIPS: add BMIPS Comtrend VR-3032u board Álvaro Fernández Rojas
13 siblings, 0 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
v5: No changes.
v4: No changes.
v3: No changes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Add PERF_BASE to cpus.
arch/mips/dts/brcm,bcm63268.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++
arch/mips/mach-bmips/Kconfig | 12 ++++++
include/configs/bmips_bcm63268.h | 25 ++++++++++++
3 files changed, 125 insertions(+)
create mode 100644 arch/mips/dts/brcm,bcm63268.dtsi
create mode 100644 include/configs/bmips_bcm63268.h
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
new file mode 100644
index 0000000..44ff888
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm63268";
+
+ cpus {
+ reg = <0x10000000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu at 0 {
+ compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu at 1 {
+ compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_cntl: syscon at 10000000 {
+ compatible = "syscon";
+ reg = <0x10000000 0x14>;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&periph_cntl>;
+ offset = <0x8>;
+ mask = <0x1>;
+ };
+
+ uart0: serial at 10000180 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x10000180 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ uart1: serial at 100001a0 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x100001a0 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ memory-controller at 10003000 {
+ compatible = "brcm,bcm6328-mc";
+ reg = <0x10003000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index ffb6ddd..6acad23 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -4,6 +4,7 @@ menu "Broadcom MIPS platforms"
config SYS_SOC
default "bcm6328" if SOC_BMIPS_BCM6328
default "bcm6358" if SOC_BMIPS_BCM6358
+ default "bcm63268" if SOC_BMIPS_BCM63268
choice
prompt "Broadcom MIPS SoC select"
@@ -30,6 +31,17 @@ config SOC_BMIPS_BCM6358
help
This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
+config SOC_BMIPS_BCM63268
+ bool "BMIPS BCM63268 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM63268 family including BCM63168, BCM63169, BCM63268 and BCM63269.
+
endchoice
choice
diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h
new file mode 100644
index 0000000..91f42e9
--- /dev/null
+++ b/include/configs/bmips_bcm63268.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM63268_H
+#define __CONFIG_BMIPS_BCM63268_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM63268_H */
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 14/14] MIPS: add BMIPS Comtrend VR-3032u board
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
` (12 preceding siblings ...)
2017-04-23 8:43 ` [U-Boot] [PATCH v5 13/14] MIPS: add support for Broadcom MIPS BCM63268 SoC family Álvaro Fernández Rojas
@ 2017-04-23 8:43 ` Álvaro Fernández Rojas
13 siblings, 0 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-23 8:43 UTC (permalink / raw)
To: u-boot
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
v5: No changes.
v4: No changes.
v3: No changes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Remove DEBUG_UART from defconfig.
arch/mips/dts/Makefile | 1 +
arch/mips/dts/comtrend,vr-3032u.dts | 27 ++++++++++++++++++++++
arch/mips/mach-bmips/Kconfig | 6 +++++
board/comtrend/vr3032u/Kconfig | 12 ++++++++++
board/comtrend/vr3032u/MAINTAINERS | 6 +++++
board/comtrend/vr3032u/Makefile | 5 ++++
board/comtrend/vr3032u/vr-3032u.c | 7 ++++++
configs/comtrend_vr3032u_ram_defconfig | 42 ++++++++++++++++++++++++++++++++++
include/configs/comtrend_vr3032u.h | 15 ++++++++++++
9 files changed, 121 insertions(+)
create mode 100644 arch/mips/dts/comtrend,vr-3032u.dts
create mode 100644 board/comtrend/vr3032u/Kconfig
create mode 100644 board/comtrend/vr3032u/MAINTAINERS
create mode 100644 board/comtrend/vr3032u/Makefile
create mode 100644 board/comtrend/vr3032u/vr-3032u.c
create mode 100644 configs/comtrend_vr3032u_ram_defconfig
create mode 100644 include/configs/comtrend_vr3032u.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 0805819..4c02c48 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
+dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts
new file mode 100644
index 0000000..c0fdb28
--- /dev/null
+++ b/arch/mips/dts/comtrend,vr-3032u.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm63268.dtsi"
+
+/ {
+ model = "Comtrend VR-3032u Board";
+ compatible = "comtrend,vr-3032u", "brcm,bcm63268";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 6acad23..5b30f3b 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -57,6 +57,11 @@ config BOARD_HUAWEI_HG556A
depends on SOC_BMIPS_BCM6358
select BMIPS_SUPPORTS_BOOT_RAM
+config BOARD_COMTREND_VR3032U
+ bool "Comtrend VR-3032u board"
+ depends on SOC_BMIPS_BCM63268
+ select BMIPS_SUPPORTS_BOOT_RAM
+
endchoice
choice
@@ -75,6 +80,7 @@ config BMIPS_SUPPORTS_BOOT_RAM
bool
source "board/comtrend/ar5387un/Kconfig"
+source "board/comtrend/vr3032u/Kconfig"
source "board/huawei/hg556a/Kconfig"
endmenu
diff --git a/board/comtrend/vr3032u/Kconfig b/board/comtrend/vr3032u/Kconfig
new file mode 100644
index 0000000..6f552cf
--- /dev/null
+++ b/board/comtrend/vr3032u/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_VR3032U
+
+config SYS_BOARD
+ default "vr3032u"
+
+config SYS_VENDOR
+ default "comtrend"
+
+config SYS_CONFIG_NAME
+ default "comtrend_vr3032u"
+
+endif
diff --git a/board/comtrend/vr3032u/MAINTAINERS b/board/comtrend/vr3032u/MAINTAINERS
new file mode 100644
index 0000000..833d7da
--- /dev/null
+++ b/board/comtrend/vr3032u/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND VR-3032U BOARD
+M: Álvaro Fernández Rojas <noltari@gmail.com>
+S: Maintained
+F: board/comtrend/vr-3032u/
+F: include/configs/comtrend_vr-3032u.h
+F: configs/comtrend_vr3032u_ram_defconfig
diff --git a/board/comtrend/vr3032u/Makefile b/board/comtrend/vr3032u/Makefile
new file mode 100644
index 0000000..9e62031
--- /dev/null
+++ b/board/comtrend/vr3032u/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += vr-3032u.o
diff --git a/board/comtrend/vr3032u/vr-3032u.c b/board/comtrend/vr3032u/vr-3032u.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/comtrend/vr3032u/vr-3032u.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig
new file mode 100644
index 0000000..4cf15b1
--- /dev/null
+++ b/configs/comtrend_vr3032u_ram_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BOARD_COMTREND_VR3032U=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u"
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SOC_BMIPS_BCM63268=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_NO_FLASH=y
+CONFIG_SYS_PROMPT="VR-3032u # "
+CONFIG_SYS_TEXT_BASE=0x80010000
diff --git a/include/configs/comtrend_vr3032u.h b/include/configs/comtrend_vr3032u.h
new file mode 100644
index 0000000..066b4c7
--- /dev/null
+++ b/include/configs/comtrend_vr3032u.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm63268.h>
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
--
2.1.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 04/14] serial: add serial driver for BCM6345
2017-04-23 8:43 ` [U-Boot] [PATCH v5 04/14] serial: add serial driver for BCM6345 Álvaro Fernández Rojas
@ 2017-04-23 20:12 ` Daniel Schwierzeck
0 siblings, 0 replies; 21+ messages in thread
From: Daniel Schwierzeck @ 2017-04-23 20:12 UTC (permalink / raw)
To: u-boot
Am 23.04.2017 um 10:43 schrieb Álvaro Fernández Rojas:
> It is based on linux/drivers/tty/serial/bcm63xx_uart.c
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
> v5: No changes.
> v4: Add more missing register configurations based on CFE.
> v3: Several improvements:
> - Add missing register configurations based on CFE.
> - Replace tabs with whitespaces.
> - Cosmetic fixes.
> v2: Introduce changes suggested by Daniel Schwierzeck:
> - Remove unneeded defines.
> - Fix incorrect multi-line comment.
>
> drivers/serial/Kconfig | 14 ++
> drivers/serial/Makefile | 1 +
> drivers/serial/serial_bcm6345.c | 311 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 326 insertions(+)
> create mode 100644 drivers/serial/serial_bcm6345.c
>
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index c0ec2ec..ca776d8 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -134,6 +134,14 @@ config DEBUG_UART_ATMEL
> will need to provide parameters to make this work. The driver will
> be available until the real driver-model serial is running.
>
> +config DEBUG_UART_BCM6345
> + bool "BCM6345 UART"
> + depends on BCM6345_SERIAL
> + help
> + Select this to enable a debug UART on BCM6345 SoCs. You
> + will need to provide parameters to make this work. The driver will
> + be available until the real driver model serial is running.
> +
> config DEBUG_UART_NS16550
> bool "ns16550"
> help
> @@ -339,6 +347,12 @@ config ATMEL_USART
> configured in the device tree, and input clock frequency can
> be got from the clk node.
>
> +config BCM6345_SERIAL
> + bool "Support for BCM6345 UART"
> + depends on DM_SERIAL
depends on DM_SERIAL && ARCH_BMIPS
> + help
> + Select this to enable UART on BCM6345 SoCs.
> +
> config FSL_LPUART
> bool "Freescale LPUART support"
> help
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index 4382cf9..dca31b2 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
> obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
> obj-$(CONFIG_ARM_DCC) += arm_dcc.o
> obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
> +obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
> obj-$(CONFIG_EFI_APP) += serial_efi.o
> obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
> obj-$(CONFIG_MCFUART) += mcfuart.o
> diff --git a/drivers/serial/serial_bcm6345.c b/drivers/serial/serial_bcm6345.c
> new file mode 100644
> index 0000000..e4d3497
> --- /dev/null
> +++ b/drivers/serial/serial_bcm6345.c
> @@ -0,0 +1,311 @@
> +/*
> + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
> + *
> + * Derived from linux/drivers/tty/serial/bcm63xx_uart.c:
> + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <clk.h>
> +#include <debug_uart.h>
> +#include <errno.h>
> +#include <serial.h>
> +#include <asm/io.h>
> +#include <asm/types.h>
> +#include <dm/device.h>
> +
> +/* UART Control register */
> +#define UART_CTL_REG 0x0
> +#define UART_CTL_RXTIMEOUT_MASK 0x1f
> +#define UART_CTL_RSTRXFIFO_SHIFT 6
> +#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
> +#define UART_CTL_RSTTXFIFO_SHIFT 7
> +#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
> +#define UART_CTL_STOPBITS_SHIFT 8
> +#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
> +#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
> +#define UART_CTL_BITSPERSYM_SHIFT 12
> +#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
> +#define UART_CTL_XMITBRK_SHIFT 14
> +#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
> +#define UART_CTL_RSVD_SHIFT 15
> +#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
> +#define UART_CTL_RXPAREVEN_SHIFT 16
> +#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
> +#define UART_CTL_RXPAREN_SHIFT 17
> +#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
> +#define UART_CTL_TXPAREVEN_SHIFT 18
> +#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
> +#define UART_CTL_TXPAREN_SHIFT 19
> +#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
> +#define UART_CTL_LOOPBACK_SHIFT 20
> +#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
> +#define UART_CTL_RXEN_SHIFT 21
> +#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
> +#define UART_CTL_TXEN_SHIFT 22
> +#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
> +#define UART_CTL_BRGEN_SHIFT 23
> +#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
> +
> +/* UART Baudword register */
> +#define UART_BAUD_REG 0x4
> +
> +/* UART FIFO Config register */
> +#define UART_FIFO_CFG_REG 0x8
> +#define UART_FIFO_CFG_RX_SHIFT 8
> +#define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT)
> +#define UART_FIFO_CFG_TX_SHIFT 12
> +#define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT)
> +
> +/* UART Interrupt register */
> +#define UART_IR_REG 0x10
> +#define UART_IR_STAT(x) (1 << (x))
> +#define UART_IR_TXEMPTY 5
> +#define UART_IR_RXOVER 7
> +#define UART_IR_RXNOTEMPTY 11
> +
> +/* UART FIFO register */
> +#define UART_FIFO_REG 0x14
> +#define UART_FIFO_VALID_MASK 0xff
> +#define UART_FIFO_FRAMEERR_SHIFT 8
> +#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
> +#define UART_FIFO_PARERR_SHIFT 9
> +#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
> +#define UART_FIFO_BRKDET_SHIFT 10
> +#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
> +#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
> + UART_FIFO_PARERR_MASK | \
> + UART_FIFO_BRKDET_MASK)
> +
> +struct bcm6345_serial_priv {
> + void __iomem *base;
> + ulong uartclk;
> +};
> +
> +/*
> + * enable rx & tx operation on uart
> + */
> +static void bcm6345_serial_enable(void __iomem *base)
> +{
> + u32 val;
> +
> + val = __raw_readl(base + UART_CTL_REG);
> + val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
> + __raw_writel(val, base + UART_CTL_REG);
please use the generic I/O accessors like readl and setbits_32 (or
readl_be and setbits_be32 since you have selected CONFIG_SWAP_IO_SPACE
in your SoC config).
This would be shorter and cleaner:
static void bcm6345_serial_enable(void __iomem *base)
{
setbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
}
> +}
> +
> +/*
> + * disable rx & tx operation on uart
> + */
> +static void bcm6345_serial_disable(void __iomem *base)
> +{
> + u32 val;
> +
> + val = __raw_readl(base + UART_CTL_REG);
> + val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
> + UART_CTL_RXEN_MASK);
> + __raw_writel(val, base + UART_CTL_REG);
> +}
> +
> +/*
> + * clear all unread data in rx fifo and unsent data in tx fifo
> + */
> +static void bcm6345_serial_flush(void __iomem *base)
> +{
> + u32 val;
> +
> + /* empty rx and tx fifo */
> + val = __raw_readl(base + UART_CTL_REG);
> + val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
> + __raw_writel(val, base + UART_CTL_REG);
> +
> + /* read any pending char to make sure all irq status are cleared */
> + __raw_readl(base + UART_FIFO_REG);
> +}
> +
> +static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
> +{
> + u32 val;
> +
> + /* mask all irq and flush port */
> + bcm6345_serial_disable(base);
> + bcm6345_serial_flush(base);
> +
> + val = __raw_readl(base + UART_CTL_REG);
> + /* set rx timeout */
> + val &= ~UART_CTL_RXTIMEOUT_MASK;
> + val |= 0x5;
> + /* set stop bits */
> + val &= ~UART_CTL_STOPBITS_MASK;
> + val |= UART_CTL_STOPBITS_1;
> + /* set bits per symbol */
> + val &= ~UART_CTL_BITSPERSYM_MASK;
> + val |= (3 << UART_CTL_BITSPERSYM_SHIFT);
> + /* clear xmit break */
> + val &= ~UART_CTL_XMITBRK_MASK;
> + /* clear reserved bit */
> + val &= ~UART_CTL_RSVD_MASK;
> + /* disable parity */
> + val |= UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK;
> + val &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
> + /* disable loopback */
> + val &= ~UART_CTL_LOOPBACK_MASK;
> + __raw_writel(val, base + UART_CTL_REG);
> +
> + val = __raw_readl(base + UART_FIFO_CFG_REG);
> + /* set rx fifo config */
> + val &= ~UART_FIFO_CFG_RX_MASK;
> + val |= (4 << UART_FIFO_CFG_RX_SHIFT);
> + /* set tx fifo config */
> + val &= ~UART_FIFO_CFG_TX_MASK;
> + val |= (4 << UART_FIFO_CFG_TX_SHIFT);
> + __raw_writel(val, base + UART_FIFO_CFG_REG);
> +
> + /* set baud rate */
> + val = (clk / baudrate) / 16;
> + if (val & 0x1)
> + val = val;
> + else
> + val = val / 2 - 1;
> + __raw_writel(val, base + UART_BAUD_REG);
> +
> + /* clear interrupts */
> + __raw_writel(0, base + UART_IR_REG);
> +
> + /* enable uart */
> + bcm6345_serial_enable(base);
> +
> + return 0;
> +}
> +
> +static int bcm6345_serial_pending(struct udevice *dev, bool input)
> +{
> + struct bcm6345_serial_priv *priv = dev_get_priv(dev);
> + u32 val = __raw_readl(priv->base + UART_IR_REG);
> +
> + if (input)
> + return (val & UART_IR_STAT(UART_IR_RXNOTEMPTY)) ? 1 : 0;
> + else
> + return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 0 : 1;
> +}
> +
> +static int bcm6345_serial_setbrg(struct udevice *dev, int baudrate)
> +{
> + struct bcm6345_serial_priv *priv = dev_get_priv(dev);
> +
> + return bcm6345_serial_init(priv->base, priv->uartclk, baudrate);
> +}
> +
> +static int bcm6345_serial_putc(struct udevice *dev, const char ch)
> +{
> + struct bcm6345_serial_priv *priv = dev_get_priv(dev);
> + u32 val;
> +
> + val = __raw_readl(priv->base + UART_IR_REG);
> + if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
> + return -EAGAIN;
> +
> + __raw_writel(ch, priv->base + UART_FIFO_REG);
> +
> + return 0;
> +}
> +
> +static int bcm6345_serial_getc(struct udevice *dev)
> +{
> + struct bcm6345_serial_priv *priv = dev_get_priv(dev);
> + u32 val;
> +
> + val = __raw_readl(priv->base + UART_IR_REG);
> + if (val & UART_IR_STAT(UART_IR_RXOVER)) {
> + /* fifo reset is required to clear interrupt */
> + val = __raw_readl(priv->base + UART_CTL_REG);
> + val |= UART_CTL_RSTRXFIFO_MASK;
> + __raw_writel(val, priv->base + UART_CTL_REG);
> + }
> + if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
> + return -EAGAIN;
> +
> + val = __raw_readl(priv->base + UART_FIFO_REG);
> + if (val & UART_FIFO_ANYERR_MASK)
> + return -EAGAIN;
> +
> + return (val & UART_FIFO_VALID_MASK);
checkpatch.pl: ERROR: return is not a function, parentheses are not required
> +}
> +
> +static int bcm6345_serial_probe(struct udevice *dev)
> +{
> + struct bcm6345_serial_priv *priv = dev_get_priv(dev);
> + struct clk clk;
> + fdt_addr_t addr;
> + fdt_size_t size;
> + int ret;
> +
> + /* get address */
> + addr = dev_get_addr_size_index(dev, 0, &size);
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + priv->base = ioremap(addr, size);
> +
> + /* get clock rate */
> + ret = clk_get_by_index(dev, 0, &clk);
> + if (ret < 0)
> + return ret;
> + priv->uartclk = clk_get_rate(&clk) / 2;
> + clk_free(&clk);
> +
> + /* initialize serial */
> + return bcm6345_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
> +}
> +
> +static const struct dm_serial_ops bcm6345_serial_ops = {
> + .putc = bcm6345_serial_putc,
> + .pending = bcm6345_serial_pending,
> + .getc = bcm6345_serial_getc,
> + .setbrg = bcm6345_serial_setbrg,
> +};
> +
> +static const struct udevice_id bcm6345_serial_ids[] = {
> + { .compatible = "brcm,bcm6345-uart" },
> + { /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(bcm6345_serial) = {
> + .name = "bcm6345-uart",
> + .id = UCLASS_SERIAL,
> + .of_match = bcm6345_serial_ids,
> + .probe = bcm6345_serial_probe,
> + .priv_auto_alloc_size = sizeof(struct bcm6345_serial_priv),
> + .ops = &bcm6345_serial_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +#ifdef CONFIG_DEBUG_UART_BCM6345
> +static inline void _debug_uart_init(void)
> +{
> + void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
> +
> + bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
> +}
> +
> +static inline void wait_xfered(void __iomem *base)
> +{
> + do {
> + u32 val = __raw_readl(base + UART_IR_REG);
> + if (val & UART_IR_STAT(UART_IR_TXEMPTY))
> + break;
> + } while (1);
> +}
> +
> +static inline void _debug_uart_putc(int ch)
> +{
> + void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
> +
> + wait_xfered(base);
> + __raw_writel(ch, base + UART_FIFO_REG);
> + wait_xfered(base);
> +}
> +
> +DEBUG_UART_FUNCS
> +#endif
>
--
- Daniel
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20170423/7741fbda/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 02/14] sysreset: add syscon-reboot driver
2017-04-23 8:43 ` [U-Boot] [PATCH v5 02/14] sysreset: add syscon-reboot driver Álvaro Fernández Rojas
@ 2017-04-23 20:16 ` Daniel Schwierzeck
0 siblings, 0 replies; 21+ messages in thread
From: Daniel Schwierzeck @ 2017-04-23 20:16 UTC (permalink / raw)
To: u-boot
Am 23.04.2017 um 10:43 schrieb Álvaro Fernández Rojas:
> Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c,
> which provides a generic driver for platforms that only require writing a mask
> to a regmap offset.
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
> v5: No chnages.
> v4: Rebased.
> v3: Introduce changes suggested by Simon Glass:
> - Add missing driver description.
> - Alphabetically order includes.
> - Add priv struct to store regmap during probe.
> - Cosmetic fixes.
> v2: No changes.
>
> drivers/sysreset/Kconfig | 8 ++++
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_syscon.c | 76 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 85 insertions(+)
> create mode 100644 drivers/sysreset/sysreset_syscon.c
>
> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
> index 9664630..b2f7464 100644
> --- a/drivers/sysreset/Kconfig
> +++ b/drivers/sysreset/Kconfig
> @@ -23,4 +23,12 @@ config SYSRESET_PSCI
> must be running on your system.
>
> endif
> +
> +config SYSRESET_SYSCON
> + bool "Enable support for mfd syscon reboot driver"
> + select REGMAP
> + select SYSCON
> + help
> + Reboot support for generic SYSCON mapped register reset.
> +
> endmenu
> diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
> index 7bb8406..bd352e7 100644
> --- a/drivers/sysreset/Makefile
> +++ b/drivers/sysreset/Makefile
> @@ -6,6 +6,7 @@
>
> obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
> obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
> +obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
>
> ifndef CONFIG_SPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
> diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c
> new file mode 100644
> index 0000000..adfddb4
> --- /dev/null
> +++ b/drivers/sysreset/sysreset_syscon.c
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
> + *
> + * Derived from linux/drivers/power/reset/syscon-reboot.c:
> + * Copyright (C) 2013, Applied Micro Circuits Corporation
> + * Author: Feng Kan <fkan@apm.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <regmap.h>
> +#include <sysreset.h>
> +#include <syscon.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct syscon_reboot_priv {
> + struct regmap *regmap;
> + unsigned int offset;
> + unsigned int mask;
> +};
> +
> +static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type)
> +{
> + struct syscon_reboot_priv *priv = dev_get_priv(dev);
> +
> + regmap_write(priv->regmap, priv->offset, priv->mask);
> +
> + return -EINPROGRESS;
> +}
> +
> +static struct sysreset_ops syscon_reboot_ops = {
> + .request = syscon_reboot_request,
> +};
> +
> +int syscon_reboot_probe(struct udevice *dev)
> +{
> + struct udevice *syscon;
> + struct syscon_reboot_priv *priv = dev_get_priv(dev);
> + int err;
> +
> + err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
> + "regmap", &syscon);
> + if (err) {
> + error("unable to find syscon device\n");
> + return err;
> + }
> +
> + priv->regmap = syscon_get_regmap(syscon);
> + if (!priv->regmap) {
> + error("unable to find regmap\n");
> + return -ENODEV;
> + }
> +
> + priv->offset = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "offset", 0);
> + priv->mask = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "mask", 0);
checkpatch.pl: WARNING: line over 80 characters
> +
> + return 0;
> +}
> +
> +static const struct udevice_id syscon_reboot_ids[] = {
> + { .compatible = "syscon-reboot" },
> + { /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(syscon_reboot) = {
> + .name = "syscon_reboot",
> + .id = UCLASS_SYSRESET,
> + .of_match = syscon_reboot_ids,
> + .probe = syscon_reboot_probe,
> + .priv_auto_alloc_size = sizeof(struct syscon_reboot_priv),
> + .ops = &syscon_reboot_ops,
> +};
>
--
- Daniel
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20170423/e47e0dd3/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 08/14] MIPS: add initial infrastructure for Broadcom MIPS SoCs
2017-04-23 8:43 ` [U-Boot] [PATCH v5 08/14] MIPS: add initial infrastructure " Álvaro Fernández Rojas
@ 2017-04-23 20:23 ` Daniel Schwierzeck
2017-04-24 10:25 ` Álvaro Fernández Rojas
0 siblings, 1 reply; 21+ messages in thread
From: Daniel Schwierzeck @ 2017-04-23 20:23 UTC (permalink / raw)
To: u-boot
Am 23.04.2017 um 10:43 schrieb Álvaro Fernández Rojas:
> CFE checks CPU Thread in a different way (using register $22):
> mfc0 t1, C0_BCM_CONFIG, 3 # $22
> li t2, CP0_CMT_TPID # (1 << 31)
> and t1, t2
> bnez t1, 2f # if we are running on thread 1, skip init
> nop
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
> v4: No changes.
> v5: No changes.
> v3: Select CONFIG_REMAKE_ELF.
> v2: Introduce changes suggested by Daniel Schwierzeck:
> - Split BMIPS support patches.
> - Replace initdram with dram_init.
> - Merge with "fix first CPU check" patch.
>
> arch/mips/Kconfig | 10 ++++++++++
> arch/mips/Makefile | 1 +
> arch/mips/cpu/start.S | 5 +++++
> arch/mips/mach-bmips/Kconfig | 22 ++++++++++++++++++++++
> arch/mips/mach-bmips/Makefile | 5 +++++
> arch/mips/mach-bmips/dram.c | 37 +++++++++++++++++++++++++++++++++++++
> include/configs/bmips_common.h | 27 +++++++++++++++++++++++++++
> 7 files changed, 107 insertions(+)
> create mode 100644 arch/mips/mach-bmips/Kconfig
> create mode 100644 arch/mips/mach-bmips/Makefile
> create mode 100644 arch/mips/mach-bmips/dram.c
> create mode 100644 include/configs/bmips_common.h
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index d97930e..c97ea41 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -75,6 +75,15 @@ config ARCH_ATH79
> select OF_CONTROL
> select DM
>
> +config ARCH_BMIPS
> + bool "Support BMIPS SoCs"
> + select OF_CONTROL
> + select DM
> + select CLK
> + select CPU
> + select RAM
> + select SYSRESET
> +
> config MACH_PIC32
> bool "Support Microchip PIC32"
> select OF_CONTROL
> @@ -123,6 +132,7 @@ source "board/micronas/vct/Kconfig"
> source "board/pb1x00/Kconfig"
> source "board/qemu-mips/Kconfig"
> source "arch/mips/mach-ath79/Kconfig"
> +source "arch/mips/mach-bmips/Kconfig"
> source "arch/mips/mach-pic32/Kconfig"
>
> if MIPS
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index efe7e44..c30d4ef 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -15,6 +15,7 @@ libs-y += arch/mips/lib/
>
> machine-$(CONFIG_SOC_AU1X00) += au1x00
> machine-$(CONFIG_ARCH_ATH79) += ath79
> +machine-$(CONFIG_ARCH_BMIPS) += bmips
> machine-$(CONFIG_MACH_PIC32) += pic32
>
> machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
> diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
> index f7dee81..5c1ad00 100644
> --- a/arch/mips/cpu/start.S
> +++ b/arch/mips/cpu/start.S
> @@ -151,8 +151,13 @@ reset:
> mfc0 t0, CP0_GLOBALNUMBER
> #endif
>
> +#ifdef CONFIG_ARCH_BMIPS
> +1: mfc0 t0, CP0_DIAGNOSTIC, 3
> + and t0, t0, (1 << 31)
> +#else
> 1: mfc0 t0, CP0_EBASE
> and t0, t0, EBASE_CPUNUM
> +#endif
>
> /* Hang if this isn't the first CPU in the system */
> 2: beqz t0, 4f
> diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
> new file mode 100644
> index 0000000..42a7e41
> --- /dev/null
> +++ b/arch/mips/mach-bmips/Kconfig
> @@ -0,0 +1,22 @@
> +menu "Broadcom MIPS platforms"
> + depends on ARCH_BMIPS
> +
> +config SYS_SOC
> + default "none"
> +
> +choice
> + prompt "Boot mode"
> +
> +config BMIPS_BOOT_RAM
> + bool "RAM boot"
> + depends on BMIPS_SUPPORTS_BOOT_RAM
> + help
> + This builds an image that is linked to a RAM address. Caches are
> + disabled and environment is built in.
maybe you should rename the Kconfig symbol and rephrase the help text.
You want to have a stage2 loader in ELF format. For this, caches
shouldn't be disabled or touched at all. Also it's up to the user if he
wants a persistent environment in flash.
> +
> +endchoice
> +
> +config BMIPS_SUPPORTS_BOOT_RAM
> + bool
> +
> +endmenu
> diff --git a/arch/mips/mach-bmips/Makefile b/arch/mips/mach-bmips/Makefile
> new file mode 100644
> index 0000000..f432acc
> --- /dev/null
> +++ b/arch/mips/mach-bmips/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += dram.o
> diff --git a/arch/mips/mach-bmips/dram.c b/arch/mips/mach-bmips/dram.c
> new file mode 100644
> index 0000000..b19b28a
> --- /dev/null
> +++ b/arch/mips/mach-bmips/dram.c
> @@ -0,0 +1,37 @@
> +/*
> + * Copyright (C) 2016 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
> + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <ram.h>
> +#include <dm.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + struct ram_info ram;
> + struct udevice *dev;
> + int err;
> +
> + err = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (err) {
> + debug("DRAM init failed: %d\n", err);
> + return 0;
> + }
> +
> + err = ram_get_info(dev, &ram);
> + if (err) {
> + debug("Cannot get DRAM size: %d\n", err);
> + return 0;
> + }
> +
> + debug("SDRAM base=%zx, size=%x\n", ram.base, ram.size);
> +
> + gd->ram_size = ram.size;
> +
> + return 0;
> +}
> diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h
> new file mode 100644
> index 0000000..3d67729
> --- /dev/null
> +++ b/include/configs/bmips_common.h
> @@ -0,0 +1,27 @@
> +/*
> + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_BMIPS_COMMON_H
> +#define __CONFIG_BMIPS_COMMON_H
> +
> +/* RAM */
> +#define CONFIG_SYS_MEMTEST_START 0xa0000000
> +#define CONFIG_SYS_MEMTEST_END 0xa2000000
> +
> +/* Serial */
> +#define CONFIG_BAUDRATE 115200
> +
> +/* Memory usage */
> +#define CONFIG_SYS_MAXARGS 24
> +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
> +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
> +#define CONFIG_SYS_CBSIZE 512
> +
> +/* U-Boot */
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +#define CONFIG_REMAKE_ELF
> +
> +#endif /* __CONFIG_BMIPS_COMMON_H */
>
--
- Daniel
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20170423/c428988c/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 05/14] cmd: cpu: refactor to ensure devices are probed and improve code style
2017-04-23 8:43 ` [U-Boot] [PATCH v5 05/14] cmd: cpu: refactor to ensure devices are probed and improve code style Álvaro Fernández Rojas
@ 2017-04-24 3:39 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2017-04-24 3:39 UTC (permalink / raw)
To: u-boot
On 23 April 2017 at 02:43, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> Use uclass_first_device and uclass_next_device in order to avoid exceptions
> for drivers that aren't probed when cpu ops are requested.
> Improve code style and fix indentations.
> Fix incorrect line break when cpu info is not available.
> Remove unneeded brackets.
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
> v5: No changes.
> v4: Refactor code to use uclass_first_device and uclass_next_device as
> requested by Simon Glass.
> v3: add new patch to ensure that device is probed.
>
> cmd/cpu.c | 30 +++++++++++++-----------------
> 1 file changed, 13 insertions(+), 17 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 06/14] cpu: add CPU driver for Broadcom MIPS SoCs
2017-04-23 8:43 ` [U-Boot] [PATCH v5 06/14] cpu: add CPU driver for Broadcom MIPS SoCs Álvaro Fernández Rojas
@ 2017-04-24 3:39 ` Simon Glass
0 siblings, 0 replies; 21+ messages in thread
From: Simon Glass @ 2017-04-24 3:39 UTC (permalink / raw)
To: u-boot
On 23 April 2017 at 02:43, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
> v5: Add specific desc functions.
> v4: No changes.
> v3: Several improvements:
> - Probe driver correctly.
> - Allocate size for priv struct.
> - Cosmetic fixes.
> v2: Introduce changes suggested by Daniel Schwierzeck:
> - Split BMIPS support patches.
> - Get register base from DT.
>
> drivers/cpu/Makefile | 2 +
> drivers/cpu/bmips_cpu.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 312 insertions(+)
> create mode 100644 drivers/cpu/bmips_cpu.c
Reviewed-by: Simon Glass <sjg@chromium.org>
But please use readl() instead of __raw_readl()
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5 08/14] MIPS: add initial infrastructure for Broadcom MIPS SoCs
2017-04-23 20:23 ` Daniel Schwierzeck
@ 2017-04-24 10:25 ` Álvaro Fernández Rojas
0 siblings, 0 replies; 21+ messages in thread
From: Álvaro Fernández Rojas @ 2017-04-24 10:25 UTC (permalink / raw)
To: u-boot
Hi Daniel,
I'm not using it as a second stage loader yet, but I plan to do that in the future (or at least on 63268 NAND devices).Right now I'm testing BMIPS support by booting u-boot.elf from RAM (loaded via TFTP from CFE bootloader).
On the other hand, I haven't yet checked what CFE loads from NAND on 63268 devices, but it's probably a bin cferam and not an elf.However, I can describe you what I think I know from 63268 devices:- They boot from a minimal CFE version stored in NAND (stage 1 CFE or cferom).- Then, CFE reads a JFFS2 partition from and loads a second stage CFE (or cferam). This is the one I plan to replace with u-boot since there's no documentation available for 63268 low level init.- After that, cferam loads and boots linux from that same JFFS2 partition where cferam is stored.
So, I still think that BMIPS_BOOT_RAM is appropriate, but you're right about changing the description.
BTW, sorry for sending this email in HTML, but I can only send it from my phone right now.
Regards,Álvaro.
On Sun, Apr 23, 2017 at 10:23 PM +0200, "Daniel Schwierzeck" <daniel.schwierzeck@gmail.com> wrote:
Am 23.04.2017 um 10:43 schrieb Álvaro Fernández Rojas:
> CFE checks CPU Thread in a different way (using register $22):
> mfc0 t1, C0_BCM_CONFIG, 3 # $22
> li t2, CP0_CMT_TPID # (1 << 31)
> and t1, t2
> bnez t1, 2f # if we are running on thread 1, skip init
> nop
>
> Signed-off-by: Álvaro Fernández Rojas
> ---
> v4: No changes.
> v5: No changes.
> v3: Select CONFIG_REMAKE_ELF.
> v2: Introduce changes suggested by Daniel Schwierzeck:
> - Split BMIPS support patches.
> - Replace initdram with dram_init.
> - Merge with "fix first CPU check" patch.
>
> arch/mips/Kconfig | 10 ++++++++++
> arch/mips/Makefile | 1 +
> arch/mips/cpu/start.S | 5 +++++
> arch/mips/mach-bmips/Kconfig | 22 ++++++++++++++++++++++
> arch/mips/mach-bmips/Makefile | 5 +++++
> arch/mips/mach-bmips/dram.c | 37 +++++++++++++++++++++++++++++++++++++
> include/configs/bmips_common.h | 27 +++++++++++++++++++++++++++
> 7 files changed, 107 insertions(+)
> create mode 100644 arch/mips/mach-bmips/Kconfig
> create mode 100644 arch/mips/mach-bmips/Makefile
> create mode 100644 arch/mips/mach-bmips/dram.c
> create mode 100644 include/configs/bmips_common.h
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index d97930e..c97ea41 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -75,6 +75,15 @@ config ARCH_ATH79
> select OF_CONTROL
> select DM
>
> +config ARCH_BMIPS
> + bool "Support BMIPS SoCs"
> + select OF_CONTROL
> + select DM
> + select CLK
> + select CPU
> + select RAM
> + select SYSRESET
> +
> config MACH_PIC32
> bool "Support Microchip PIC32"
> select OF_CONTROL
> @@ -123,6 +132,7 @@ source "board/micronas/vct/Kconfig"
> source "board/pb1x00/Kconfig"
> source "board/qemu-mips/Kconfig"
> source "arch/mips/mach-ath79/Kconfig"
> +source "arch/mips/mach-bmips/Kconfig"
> source "arch/mips/mach-pic32/Kconfig"
>
> if MIPS
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index efe7e44..c30d4ef 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -15,6 +15,7 @@ libs-y += arch/mips/lib/
>
> machine-$(CONFIG_SOC_AU1X00) += au1x00
> machine-$(CONFIG_ARCH_ATH79) += ath79
> +machine-$(CONFIG_ARCH_BMIPS) += bmips
> machine-$(CONFIG_MACH_PIC32) += pic32
>
> machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
> diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
> index f7dee81..5c1ad00 100644
> --- a/arch/mips/cpu/start.S
> +++ b/arch/mips/cpu/start.S
> @@ -151,8 +151,13 @@ reset:
> mfc0 t0, CP0_GLOBALNUMBER
> #endif
>
> +#ifdef CONFIG_ARCH_BMIPS
> +1: mfc0 t0, CP0_DIAGNOSTIC, 3
> + and t0, t0, (1 << 31)
> +#else
> 1: mfc0 t0, CP0_EBASE
> and t0, t0, EBASE_CPUNUM
> +#endif
>
> /* Hang if this isn't the first CPU in the system */
> 2: beqz t0, 4f
> diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
> new file mode 100644
> index 0000000..42a7e41
> --- /dev/null
> +++ b/arch/mips/mach-bmips/Kconfig
> @@ -0,0 +1,22 @@
> +menu "Broadcom MIPS platforms"
> + depends on ARCH_BMIPS
> +
> +config SYS_SOC
> + default "none"
> +
> +choice
> + prompt "Boot mode"
> +
> +config BMIPS_BOOT_RAM
> + bool "RAM boot"
> + depends on BMIPS_SUPPORTS_BOOT_RAM
> + help
> + This builds an image that is linked to a RAM address. Caches are
> + disabled and environment is built in.
maybe you should rename the Kconfig symbol and rephrase the help text.
You want to have a stage2 loader in ELF format. For this, caches
shouldn't be disabled or touched at all. Also it's up to the user if he
wants a persistent environment in flash.
> +
> +endchoice
> +
> +config BMIPS_SUPPORTS_BOOT_RAM
> + bool
> +
> +endmenu
> diff --git a/arch/mips/mach-bmips/Makefile b/arch/mips/mach-bmips/Makefile
> new file mode 100644
> index 0000000..f432acc
> --- /dev/null
> +++ b/arch/mips/mach-bmips/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += dram.o
> diff --git a/arch/mips/mach-bmips/dram.c b/arch/mips/mach-bmips/dram.c
> new file mode 100644
> index 0000000..b19b28a
> --- /dev/null
> +++ b/arch/mips/mach-bmips/dram.c
> @@ -0,0 +1,37 @@
> +/*
> + * Copyright (C) 2016 Daniel Schwierzeck
> + * Copyright (C) 2017 Álvaro Fernández Rojas
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + struct ram_info ram;
> + struct udevice *dev;
> + int err;
> +
> + err = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (err) {
> + debug("DRAM init failed: %d
", err);
> + return 0;
> + }
> +
> + err = ram_get_info(dev, &ram);
> + if (err) {
> + debug("Cannot get DRAM size: %d
", err);
> + return 0;
> + }
> +
> + debug("SDRAM base=%zx, size=%x
", ram.base, ram.size);
> +
> + gd->ram_size = ram.size;
> +
> + return 0;
> +}
> diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h
> new file mode 100644
> index 0000000..3d67729
> --- /dev/null
> +++ b/include/configs/bmips_common.h
> @@ -0,0 +1,27 @@
> +/*
> + * Copyright (C) 2017 Álvaro Fernández Rojas
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_BMIPS_COMMON_H
> +#define __CONFIG_BMIPS_COMMON_H
> +
> +/* RAM */
> +#define CONFIG_SYS_MEMTEST_START 0xa0000000
> +#define CONFIG_SYS_MEMTEST_END 0xa2000000
> +
> +/* Serial */
> +#define CONFIG_BAUDRATE 115200
> +
> +/* Memory usage */
> +#define CONFIG_SYS_MAXARGS 24
> +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
> +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
> +#define CONFIG_SYS_CBSIZE 512
> +
> +/* U-Boot */
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +#define CONFIG_REMAKE_ELF
> +
> +#endif /* __CONFIG_BMIPS_COMMON_H */
>
--
- Daniel
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2017-04-24 10:25 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-23 8:43 [U-Boot] [PATCH v5 00/14] Add support for Broadcom MIPS SoCs Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 01/14] cmd: cpu: fix NULL cpu feature prints Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 02/14] sysreset: add syscon-reboot driver Álvaro Fernández Rojas
2017-04-23 20:16 ` Daniel Schwierzeck
2017-04-23 8:43 ` [U-Boot] [PATCH v5 03/14] MIPS: allow using generic sysreset drivers Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 04/14] serial: add serial driver for BCM6345 Álvaro Fernández Rojas
2017-04-23 20:12 ` Daniel Schwierzeck
2017-04-23 8:43 ` [U-Boot] [PATCH v5 05/14] cmd: cpu: refactor to ensure devices are probed and improve code style Álvaro Fernández Rojas
2017-04-24 3:39 ` Simon Glass
2017-04-23 8:43 ` [U-Boot] [PATCH v5 06/14] cpu: add CPU driver for Broadcom MIPS SoCs Álvaro Fernández Rojas
2017-04-24 3:39 ` Simon Glass
2017-04-23 8:43 ` [U-Boot] [PATCH v5 07/14] ram: add RAM " Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 08/14] MIPS: add initial infrastructure " Álvaro Fernández Rojas
2017-04-23 20:23 ` Daniel Schwierzeck
2017-04-24 10:25 ` Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 09/14] MIPS: add support for Broadcom MIPS BCM6358 SoC family Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 10/14] MIPS: add BMIPS Huawei HG556a board Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 11/14] MIPS: add support for Broadcom MIPS BCM6328 SoC family Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 12/14] MIPS: add BMIPS Comtrend AR-5387un board Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 13/14] MIPS: add support for Broadcom MIPS BCM63268 SoC family Álvaro Fernández Rojas
2017-04-23 8:43 ` [U-Boot] [PATCH v5 14/14] MIPS: add BMIPS Comtrend VR-3032u board Álvaro Fernández Rojas
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.