From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1955778AbdDZFxn convert rfc822-to-8bit (ORCPT ); Wed, 26 Apr 2017 01:53:43 -0400 Received: from mx1.redhat.com ([209.132.183.28]:57492 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1955762AbdDZFxN (ORCPT ); Wed, 26 Apr 2017 01:53:13 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 2C4CA81F07 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=kraxel@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 2C4CA81F07 Message-ID: <1493185990.23739.7.camel@redhat.com> Subject: Re: [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format From: Gerd Hoffmann To: Michel =?ISO-8859-1?Q?D=E4nzer?= Cc: dri-devel@lists.freedesktop.org, open list , amd-gfx@lists.freedesktop.org, Daniel Vetter Date: Wed, 26 Apr 2017 07:53:10 +0200 In-Reply-To: <3b872a56-80b5-0c44-712f-a9517489eb24@daenzer.net> References: <20170424062532.26722-1-kraxel@redhat.com> <20170424062532.26722-4-kraxel@redhat.com> <3b872a56-80b5-0c44-712f-a9517489eb24@daenzer.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Mime-Version: 1.0 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Wed, 26 Apr 2017 05:53:13 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Di, 2017-04-25 at 12:18 +0900, Michel Dänzer wrote: > On 24/04/17 03:25 PM, Gerd Hoffmann wrote: > > Return correct fourcc codes on bigendian. Drivers must be adapted to > > this change. > > > > Signed-off-by: Gerd Hoffmann > > Just to reiterate, this won't work for the radeon driver, which programs > the GPU to use (effectively, per the current definition that these are > little endian GPU formats) DRM_FORMAT_XRGB8888 with pre-R600 and > DRM_FORMAT_BGRX8888 with >= R600. Hmm, ok, how does bigendian fbdev emulation work on pre-R600 then? > > +#ifdef __BIG_ENDIAN > > + switch (bpp) { > > + case 8: > > + fmt = DRM_FORMAT_C8; > > + break; > > + case 24: > > + fmt = DRM_FORMAT_BGR888; > > + break; > > BTW, endianness as a concept cannot apply to 8 or 24 bpp formats. I could move the 8 bpp case out of the #ifdef somehow, but code readability will suffer then I think ... For 24 we have different byte orderings, but yes, you can't switch from one to the other with byteswapping. Probably one of the reasons why this format is pretty much out of fashion these days ... cheers, Gerd From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gerd Hoffmann Subject: Re: [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format Date: Wed, 26 Apr 2017 07:53:10 +0200 Message-ID: <1493185990.23739.7.camel@redhat.com> References: <20170424062532.26722-1-kraxel@redhat.com> <20170424062532.26722-4-kraxel@redhat.com> <3b872a56-80b5-0c44-712f-a9517489eb24@daenzer.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <3b872a56-80b5-0c44-712f-a9517489eb24-otUistvHUpPR7s880joybQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Michel =?ISO-8859-1?Q?D=E4nzer?= Cc: Daniel Vetter , amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, open list , dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org List-Id: dri-devel@lists.freedesktop.org T24gRGksIDIwMTctMDQtMjUgYXQgMTI6MTggKzA5MDAsIE1pY2hlbCBEw6RuemVyIHdyb3RlOgo+ IE9uIDI0LzA0LzE3IDAzOjI1IFBNLCBHZXJkIEhvZmZtYW5uIHdyb3RlOgo+ID4gUmV0dXJuIGNv cnJlY3QgZm91cmNjIGNvZGVzIG9uIGJpZ2VuZGlhbi4gIERyaXZlcnMgbXVzdCBiZSBhZGFwdGVk IHRvCj4gPiB0aGlzIGNoYW5nZS4KPiA+IAo+ID4gU2lnbmVkLW9mZi1ieTogR2VyZCBIb2ZmbWFu biA8a3JheGVsQHJlZGhhdC5jb20+Cj4gCj4gSnVzdCB0byByZWl0ZXJhdGUsIHRoaXMgd29uJ3Qg d29yayBmb3IgdGhlIHJhZGVvbiBkcml2ZXIsIHdoaWNoIHByb2dyYW1zCj4gdGhlIEdQVSB0byB1 c2UgKGVmZmVjdGl2ZWx5LCBwZXIgdGhlIGN1cnJlbnQgZGVmaW5pdGlvbiB0aGF0IHRoZXNlIGFy ZQo+IGxpdHRsZSBlbmRpYW4gR1BVIGZvcm1hdHMpIERSTV9GT1JNQVRfWFJHQjg4ODggd2l0aCBw cmUtUjYwMCBhbmQKPiBEUk1fRk9STUFUX0JHUlg4ODg4IHdpdGggPj0gUjYwMC4KCkhtbSwgb2ss IGhvdyBkb2VzIGJpZ2VuZGlhbiBmYmRldiBlbXVsYXRpb24gd29yayBvbiBwcmUtUjYwMCB0aGVu PwoKPiA+ICsjaWZkZWYgX19CSUdfRU5ESUFOCj4gPiArCXN3aXRjaCAoYnBwKSB7Cj4gPiArCWNh c2UgODoKPiA+ICsJCWZtdCA9IERSTV9GT1JNQVRfQzg7Cj4gPiArCQlicmVhazsKPiA+ICsJY2Fz ZSAyNDoKPiA+ICsJCWZtdCA9IERSTV9GT1JNQVRfQkdSODg4Owo+ID4gKwkJYnJlYWs7Cj4gCj4g QlRXLCBlbmRpYW5uZXNzIGFzIGEgY29uY2VwdCBjYW5ub3QgYXBwbHkgdG8gOCBvciAyNCBicHAg Zm9ybWF0cy4KCkkgY291bGQgbW92ZSB0aGUgOCBicHAgY2FzZSBvdXQgb2YgdGhlICNpZmRlZiBz b21laG93LCBidXQgY29kZQpyZWFkYWJpbGl0eSB3aWxsIHN1ZmZlciB0aGVuIEkgdGhpbmsgLi4u CgpGb3IgMjQgd2UgaGF2ZSBkaWZmZXJlbnQgYnl0ZSBvcmRlcmluZ3MsIGJ1dCB5ZXMsIHlvdSBj YW4ndCBzd2l0Y2ggZnJvbQpvbmUgdG8gdGhlIG90aGVyIHdpdGggYnl0ZXN3YXBwaW5nLiAgUHJv YmFibHkgb25lIG9mIHRoZSByZWFzb25zIHdoeQp0aGlzIGZvcm1hdCBpcyBwcmV0dHkgbXVjaCBv dXQgb2YgZmFzaGlvbiB0aGVzZSBkYXlzIC4uLgoKY2hlZXJzLAogIEdlcmQKCl9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmFtZC1nZnggbWFpbGluZyBsaXN0 CmFtZC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Au b3JnL21haWxtYW4vbGlzdGluZm8vYW1kLWdmeAo=