From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2999595AbdDZMLZ convert rfc822-to-8bit (ORCPT ); Wed, 26 Apr 2017 08:11:25 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45170 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1954723AbdDZMLS (ORCPT ); Wed, 26 Apr 2017 08:11:18 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com EAC71C0567A3 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=kraxel@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com EAC71C0567A3 Message-ID: <1493208671.23739.19.camel@redhat.com> Subject: Re: [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format From: Gerd Hoffmann To: Michel =?ISO-8859-1?Q?D=E4nzer?= Cc: Daniel Vetter , amd-gfx@lists.freedesktop.org, open list , dri-devel@lists.freedesktop.org Date: Wed, 26 Apr 2017 14:11:11 +0200 In-Reply-To: <8f91cc58-16dc-5899-66b6-06d430a18801@daenzer.net> References: <20170424062532.26722-1-kraxel@redhat.com> <20170424062532.26722-4-kraxel@redhat.com> <3b872a56-80b5-0c44-712f-a9517489eb24@daenzer.net> <1493185990.23739.7.camel@redhat.com> <8f91cc58-16dc-5899-66b6-06d430a18801@daenzer.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Mime-Version: 1.0 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Wed, 26 Apr 2017 12:11:13 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, > >> Just to reiterate, this won't work for the radeon driver, which programs > >> the GPU to use (effectively, per the current definition that these are > >> little endian GPU formats) DRM_FORMAT_XRGB8888 with pre-R600 and > >> DRM_FORMAT_BGRX8888 with >= R600. > > > > Hmm, ok, how does bigendian fbdev emulation work on pre-R600 then? > > Using a GPU byte swapping mechanism which only affects CPU access to > video RAM. That is done using the RADEON_TILING_SWAP_{16,32}BIT flag mentioned in another thread? Ok, so the cpu view to fbdev is DRM_FORMAT_BGRX8888 in all cases. What about dumb bos? You've mentioned the swap flag isn't used for those. Which implies they are in little endian byte order (both gpu and cpu view). Does the modesetting driver work correctly on that hardware? cheers, Gerd From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gerd Hoffmann Subject: Re: [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format Date: Wed, 26 Apr 2017 14:11:11 +0200 Message-ID: <1493208671.23739.19.camel@redhat.com> References: <20170424062532.26722-1-kraxel@redhat.com> <20170424062532.26722-4-kraxel@redhat.com> <3b872a56-80b5-0c44-712f-a9517489eb24@daenzer.net> <1493185990.23739.7.camel@redhat.com> <8f91cc58-16dc-5899-66b6-06d430a18801@daenzer.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <8f91cc58-16dc-5899-66b6-06d430a18801-otUistvHUpPR7s880joybQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Michel =?ISO-8859-1?Q?D=E4nzer?= Cc: Daniel Vetter , dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, open list , amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org List-Id: dri-devel@lists.freedesktop.org ICBIaSwKCj4gPj4gSnVzdCB0byByZWl0ZXJhdGUsIHRoaXMgd29uJ3Qgd29yayBmb3IgdGhlIHJh ZGVvbiBkcml2ZXIsIHdoaWNoIHByb2dyYW1zCj4gPj4gdGhlIEdQVSB0byB1c2UgKGVmZmVjdGl2 ZWx5LCBwZXIgdGhlIGN1cnJlbnQgZGVmaW5pdGlvbiB0aGF0IHRoZXNlIGFyZQo+ID4+IGxpdHRs ZSBlbmRpYW4gR1BVIGZvcm1hdHMpIERSTV9GT1JNQVRfWFJHQjg4ODggd2l0aCBwcmUtUjYwMCBh bmQKPiA+PiBEUk1fRk9STUFUX0JHUlg4ODg4IHdpdGggPj0gUjYwMC4KPiA+IAo+ID4gSG1tLCBv aywgaG93IGRvZXMgYmlnZW5kaWFuIGZiZGV2IGVtdWxhdGlvbiB3b3JrIG9uIHByZS1SNjAwIHRo ZW4/Cj4gCj4gVXNpbmcgYSBHUFUgYnl0ZSBzd2FwcGluZyBtZWNoYW5pc20gd2hpY2ggb25seSBh ZmZlY3RzIENQVSBhY2Nlc3MgdG8KPiB2aWRlbyBSQU0uCgpUaGF0IGlzIGRvbmUgdXNpbmcgdGhl IFJBREVPTl9USUxJTkdfU1dBUF97MTYsMzJ9QklUIGZsYWcgbWVudGlvbmVkIGluCmFub3RoZXIg dGhyZWFkPwoKT2ssIHNvIHRoZSBjcHUgdmlldyB0byBmYmRldiBpcyBEUk1fRk9STUFUX0JHUlg4 ODg4IGluIGFsbCBjYXNlcy4KCldoYXQgYWJvdXQgZHVtYiBib3M/ICBZb3UndmUgbWVudGlvbmVk IHRoZSBzd2FwIGZsYWcgaXNuJ3QgdXNlZCBmb3IKdGhvc2UuICBXaGljaCBpbXBsaWVzIHRoZXkg YXJlIGluIGxpdHRsZSBlbmRpYW4gYnl0ZSBvcmRlciAoYm90aCBncHUgYW5kCmNwdSB2aWV3KS4g IERvZXMgdGhlIG1vZGVzZXR0aW5nIGRyaXZlciB3b3JrIGNvcnJlY3RseSBvbiB0aGF0IGhhcmR3 YXJlPwoKY2hlZXJzLAogIEdlcmQKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fCmFtZC1nZnggbWFpbGluZyBsaXN0CmFtZC1nZnhAbGlzdHMuZnJlZWRlc2t0 b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vYW1k LWdmeAo=