From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:09:31 +0200 Subject: [U-Boot] [PATCH v2 2/5] mips: bmips: add bcm6345-gpio driver support for BCM6358 In-Reply-To: <1494180574-14821-1-git-send-email-noltari@gmail.com> References: <1493816847-30393-1-git-send-email-noltari@gmail.com> <1494180574-14821-1-git-send-email-noltari@gmail.com> Message-ID: <1494180574-14821-3-git-send-email-noltari@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de This SoC has one gpio bank divided into two 32 bit registers, with a total of 40 GPIOs. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- v2: no changes. arch/mips/dts/brcm,bcm6358.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 48322fb..4c94555 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -73,6 +73,25 @@ mask = <0x1>; }; + gpio1: gpio-controller at fffe0080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + + status = "disabled"; + }; + + gpio0: gpio-controller at fffe0084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + uart0: serial at fffe0100 { compatible = "brcm,bcm6345-uart"; reg = <0xfffe0100 0x18>; -- 2.1.4