From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753374AbdEIHvh (ORCPT ); Tue, 9 May 2017 03:51:37 -0400 Received: from mail-bn3nam01on0085.outbound.protection.outlook.com ([104.47.33.85]:45600 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753276AbdEIHvc (ORCPT ); Tue, 9 May 2017 03:51:32 -0400 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=fail action=none header.from=nxp.com; From: Dong Aisheng To: CC: , , , , , , , , Dong Aisheng , , Rob Herring Subject: [PATCH 3/6] dt-bindings: serial: fsl-lpuart: add i.MX7ULP support Date: Tue, 9 May 2017 15:50:45 +0800 Message-ID: <1494316248-24052-4-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> 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1;BLUPR03MB167;7:d0zLpXbV5dwsTpNjFosuMeP6PIfnGcb/bba9zGqJWI517+Sx712dGh6yaWP2oDbNjrNeTY3ivP3EIJZdjr3XfmdFMTQIcI1sEd12R/YDGU2unkJQMFCJThRuuy6Is9qoryoVd4iOjVe4eWtE43MylkHF0WY1xUeaGSvAZ9HsoyzVPDeXzdf5iphN48CCNcnXCjeFZSWhrcoCkcYem2tLu2GNHAXKTpWdclbiLTRkZ+wWMsXAeF9UQ2K3MWfj8pWZx4sL5OJXs1ZFFeeYklalQXe/prXUuHcI8SltMURUQ7pqkLXBhEcidk3tLSbvAiKIKBDp0riheo+a3H2fduy25Q== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2017 07:51:15.3216 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;Ip=[192.88.168.50];Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB167 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The lpuart of imx7ulp is basically the same as ls1021a. It's also 32 bit width register, but unlike ls1021a, it's little endian. Besides that, imx7ulp lpuart has a minor different register layout from ls1021a. Cc: devicetree@vger.kernel.org Cc: Rob Herring Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: Fugang Duan Cc: Stefan Agner Cc: Mingkai Hu Cc: Yangbo Lu Signed-off-by: Dong Aisheng --- Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index c95005e..a1252a0 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -6,6 +6,8 @@ Required properties: on Vybrid vf610 SoC with 8-bit register organization - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated on LS1021A SoC with 32-bit big-endian register organization + - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated + on i.MX7ULP SoC with 32-bit little-endian register organization - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dong Aisheng Subject: [PATCH 3/6] dt-bindings: serial: fsl-lpuart: add i.MX7ULP support Date: Tue, 9 May 2017 15:50:45 +0800 Message-ID: <1494316248-24052-4-git-send-email-aisheng.dong@nxp.com> References: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, gregkh@linuxfoundation.org, jslaby@suse.com, fugang.duan@nxp.com, stefan@agner.ch, Mingkai.Hu@nxp.com, yangbo.lu@nxp.com, Dong Aisheng , devicetree@vger.kernel.org, Rob Herring List-Id: devicetree@vger.kernel.org The lpuart of imx7ulp is basically the same as ls1021a. It's also 32 bit width register, but unlike ls1021a, it's little endian. Besides that, imx7ulp lpuart has a minor different register layout from ls1021a. Cc: devicetree@vger.kernel.org Cc: Rob Herring Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: Fugang Duan Cc: Stefan Agner Cc: Mingkai Hu Cc: Yangbo Lu Signed-off-by: Dong Aisheng --- Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index c95005e..a1252a0 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -6,6 +6,8 @@ Required properties: on Vybrid vf610 SoC with 8-bit register organization - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated on LS1021A SoC with 32-bit big-endian register organization + - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated + on i.MX7ULP SoC with 32-bit little-endian register organization - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: aisheng.dong@nxp.com (Dong Aisheng) Date: Tue, 9 May 2017 15:50:45 +0800 Subject: [PATCH 3/6] dt-bindings: serial: fsl-lpuart: add i.MX7ULP support In-Reply-To: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> References: <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com> Message-ID: <1494316248-24052-4-git-send-email-aisheng.dong@nxp.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The lpuart of imx7ulp is basically the same as ls1021a. It's also 32 bit width register, but unlike ls1021a, it's little endian. Besides that, imx7ulp lpuart has a minor different register layout from ls1021a. Cc: devicetree at vger.kernel.org Cc: Rob Herring Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: Fugang Duan Cc: Stefan Agner Cc: Mingkai Hu Cc: Yangbo Lu Signed-off-by: Dong Aisheng --- Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index c95005e..a1252a0 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -6,6 +6,8 @@ Required properties: on Vybrid vf610 SoC with 8-bit register organization - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated on LS1021A SoC with 32-bit big-endian register organization + - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated + on i.MX7ULP SoC with 32-bit little-endian register organization - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names -- 2.7.4