From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753359AbdEJNpa (ORCPT ); Wed, 10 May 2017 09:45:30 -0400 Received: from cn.fujitsu.com ([59.151.112.132]:46185 "EHLO heian.cn.fujitsu.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753140AbdEJNp2 (ORCPT ); Wed, 10 May 2017 09:45:28 -0400 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="18692963" From: Dou Liyang To: , CC: , , , , , , Dou Liyang Subject: [RFC PATCH v3 05/12] x86/ioapic: Refactor the delay logic in timer_irq_works() Date: Wed, 10 May 2017 21:44:42 +0800 Message-ID: <1494423889-25799-6-git-send-email-douly.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1494423889-25799-1-git-send-email-douly.fnst@cn.fujitsu.com> References: <1494423889-25799-1-git-send-email-douly.fnst@cn.fujitsu.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.167.226.106] X-yoursite-MailScanner-ID: B815347C6105.AEFF0 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: douly.fnst@cn.fujitsu.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Kernel use timer_irq_works() to detects the timer IRQs. It calls mdelay(10) to delay ten ticks and checks whether the timer IRQs work or not. The mdelay() depends on the loops_per_jiffy which is set up in calibrate_delay(). And in "notsc" case, calibrating delay also should make sure the timer IRQs work well. Now, initializing interrupt mode behind timer init makes the timer_irq_works() in advance of calibrate_delay(). the mdelay() doesn't work well in timer_irq_works(). Refactor the delay logic by waiting for some cycles. At the system With X86_FEATURE_TSC, Use rdtsc(), others will call __delay() directly. Signed-off-by: Dou Liyang --- v2 --> v3: Find a new way to for waiting. Reference to the realization of hpet_clocksource_register() by Thomas. arch/x86/kernel/apic/io_apic.c | 46 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 347bb9f..a63c19e 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1607,6 +1607,44 @@ static int __init notimercheck(char *s) } __setup("no_timer_check", notimercheck); +static void delay_with_tsc(void) +{ + unsigned long long start, now; + unsigned long ticks = jiffies; + + start = rdtsc(); + + /* + * We don't know the TSC frequency yet, but waiting for + * 40000000000/HZ TSC cycles is safe: + * 4 GHz == 10 jiffies + * 1 GHz == 40 jiffies + */ + do { + rep_nop(); + now = rdtsc(); + } while ((now - start) < 40000000000UL / HZ && + time_before_eq(jiffies, ticks + 4)); +} + +static void delay_without_tsc(void) +{ + int band = 1; + unsigned long ticks = jiffies; + + /* + * We don't know any frequency yet, but waiting for + * 40940000000/HZ cycles is safe: + * 4 GHz == 10 jiffies + * 1 GHz == 40 jiffies + * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094 + */ + do { + __delay(((1 << band++) * 10000000UL) / HZ); + } while (band < 12 && time_before_eq(jiffies, ticks + 4)); +} + + /* * There is a nasty bug in some older SMP boards, their mptable lies * about the timer IRQ. We do the following to work around the situation: @@ -1625,8 +1663,12 @@ static int __init timer_irq_works(void) local_save_flags(flags); local_irq_enable(); - /* Let ten ticks pass... */ - mdelay((10 * 1000) / HZ); + + if (boot_cpu_has(X86_FEATURE_TSC)) + delay_with_tsc(); + else + delay_without_tsc(); + local_irq_restore(flags); /* -- 2.5.5