[U-Boot] [PATCH 0/6] mips: bmips: add BCM6348 SoC support

[U-Boot] [PATCH 0/6] mips: bmips: add BCM6348 SoC support

[Álvaro Fernández Rojas]

BCM6348 is one of the first BCM63xx SoCs and prior to BCM6358, which means
that it also needs ioremap "hacks".
Appart from that, rev a1 BCM6348 SoCs have a HW bug and it's pll_conf
register can't be used to perform reboots.

Álvaro Fernández Rojas (6):
  dm: cpu: bmips: rename cpu_desc specific functions
  dm: cpu: bmips: add BCM6348 support
  dm: ram: bmips: split bcm6358_get_ram_size
  dm: cpu: bmips: add BCM6338/BCM6348 support
  MIPS: add support for Broadcom MIPS BCM6348 SoC family
  MIPS: add BMIPS Comtrend CT-5361 board

 arch/mips/dts/Makefile                    |   1 +
 arch/mips/dts/brcm,bcm6348.dtsi           | 127 ++++++++++++++++++++++++++++++
 arch/mips/dts/comtrend,ct-5361.dts        |  49 ++++++++++++
 arch/mips/mach-bmips/Kconfig              |  18 +++++
 arch/mips/mach-bmips/include/ioremap.h    |   3 +-
 board/comtrend/ct5361/Kconfig             |  12 +++
 board/comtrend/ct5361/MAINTAINERS         |   6 ++
 board/comtrend/ct5361/Makefile            |   5 ++
 board/comtrend/ct5361/ct-5361.c           |   7 ++
 configs/comtrend_ct5361_ram_defconfig     |  57 ++++++++++++++
 drivers/cpu/bmips_cpu.c                   |  44 +++++++++--
 drivers/ram/bmips_ram.c                   |  54 ++++++++++---
 include/configs/bmips_bcm6348.h           |  30 +++++++
 include/configs/comtrend_ct5361.h         |  20 +++++
 include/dt-bindings/clock/bcm6348-clock.h |  22 ++++++
 include/dt-bindings/reset/bcm6348-reset.h |  22 ++++++
 16 files changed, 461 insertions(+), 16 deletions(-)
 create mode 100644 arch/mips/dts/brcm,bcm6348.dtsi
 create mode 100644 arch/mips/dts/comtrend,ct-5361.dts
 create mode 100644 board/comtrend/ct5361/Kconfig
 create mode 100644 board/comtrend/ct5361/MAINTAINERS
 create mode 100644 board/comtrend/ct5361/Makefile
 create mode 100644 board/comtrend/ct5361/ct-5361.c
 create mode 100644 configs/comtrend_ct5361_ram_defconfig
 create mode 100644 include/configs/bmips_bcm6348.h
 create mode 100644 include/configs/comtrend_ct5361.h
 create mode 100644 include/dt-bindings/clock/bcm6348-clock.h
 create mode 100644 include/dt-bindings/reset/bcm6348-reset.h

-- 
2.1.4

[U-Boot] [PATCH 1/6] dm: cpu: bmips: rename cpu_desc specific functions

[Álvaro Fernández Rojas]

Use a generic name for cpu_desc functions instead of using a specific SoC one.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 drivers/cpu/bmips_cpu.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 379acf2..6087163 100644
--- a/drivers/cpu/bmips_cpu.c
+++ b/drivers/cpu/bmips_cpu.c
@@ -56,7 +56,7 @@ struct bmips_cpu_priv {
 };
 
 /* Specific CPU Ops */
-static int bcm6358_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
+static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 				int size)
 {
 	unsigned short cpu_id;
@@ -72,7 +72,7 @@ static int bcm6358_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 	return 0;
 }
 
-static int bcm6328_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
+static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 				int size)
 {
 	unsigned int cpu_id;
@@ -166,19 +166,19 @@ static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 }
 
 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
-	.get_cpu_desc = bcm6328_get_cpu_desc,
+	.get_cpu_desc = bmips_long_cpu_desc,
 	.get_cpu_freq = bcm6328_get_cpu_freq,
 	.get_cpu_count = bcm6328_get_cpu_count,
 };
 
 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
-	.get_cpu_desc = bcm6358_get_cpu_desc,
+	.get_cpu_desc = bmips_short_cpu_desc,
 	.get_cpu_freq = bcm6358_get_cpu_freq,
 	.get_cpu_count = bcm6358_get_cpu_count,
 };
 
 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
-	.get_cpu_desc = bcm6328_get_cpu_desc,
+	.get_cpu_desc = bmips_long_cpu_desc,
 	.get_cpu_freq = bcm63268_get_cpu_freq,
 	.get_cpu_count = bcm6358_get_cpu_count,
 };
-- 
2.1.4

[U-Boot] [PATCH 2/6] dm: cpu: bmips: add BCM6348 support

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 drivers/cpu/bmips_cpu.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 6087163..03b503a 100644
--- a/drivers/cpu/bmips_cpu.c
+++ b/drivers/cpu/bmips_cpu.c
@@ -30,6 +30,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define STRAPBUS_6328_FCVO_SHIFT	7
 #define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
 
+#define REG_BCM6348_PERF_MIPSPLLCFG	0x34
+#define MIPSPLLCFG_6348_M1CPU_SHIFT	6
+#define MIPSPLLCFG_6348_M1CPU_MASK	(0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
+#define MIPSPLLCFG_6348_N2_SHIFT	15
+#define MIPSPLLCFG_6348_N2_MASK		(0x1F << MIPSPLLCFG_6348_N2_SHIFT)
+#define MIPSPLLCFG_6348_N1_SHIFT	20
+#define MIPSPLLCFG_6348_N1_MASK		(0x7 << MIPSPLLCFG_6348_N1_SHIFT)
+
 #define REG_BCM6358_DDR_DMIPSPLLCFG	0x12b8
 #define DMIPSPLLCFG_6358_M1_SHIFT	0
 #define DMIPSPLLCFG_6358_M1_MASK	(0xff << DMIPSPLLCFG_6358_M1_SHIFT)
@@ -115,6 +123,18 @@ static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 	}
 }
 
+static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+	unsigned int tmp, n1, n2, m1;
+
+	tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
+	n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
+	n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
+	m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
+
+	return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
+}
+
 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
 {
 	unsigned int tmp, n1, n2, m1;
@@ -160,6 +180,11 @@ static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
 		return 2;
 }
 
+static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
+{
+	return 1;
+}
+
 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 {
 	return 2;
@@ -171,6 +196,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
 	.get_cpu_count = bcm6328_get_cpu_count,
 };
 
+static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
+	.get_cpu_desc = bmips_short_cpu_desc,
+	.get_cpu_freq = bcm6348_get_cpu_freq,
+	.get_cpu_count = bcm6345_get_cpu_count,
+};
+
 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
 	.get_cpu_desc = bmips_short_cpu_desc,
 	.get_cpu_freq = bcm6358_get_cpu_freq,
@@ -262,6 +293,9 @@ static const struct udevice_id bmips_cpu_ids[] = {
 		.compatible = "brcm,bcm6328-cpu",
 		.data = (ulong)&bmips_cpu_bcm6328,
 	}, {
+		.compatible = "brcm,bcm6348-cpu",
+		.data = (ulong)&bmips_cpu_bcm6348,
+	}, {
 		.compatible = "brcm,bcm6358-cpu",
 		.data = (ulong)&bmips_cpu_bcm6358,
 	}, {
-- 
2.1.4

[U-Boot] [PATCH 3/6] dm: ram: bmips: split bcm6358_get_ram_size

[Álvaro Fernández Rojas]

This is done in order to reuse ram size calculation for BCM6338/BCM6348

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 drivers/ram/bmips_ram.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c
index d0f7cd7..382e231 100644
--- a/drivers/ram/bmips_ram.c
+++ b/drivers/ram/bmips_ram.c
@@ -40,24 +40,27 @@ static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
 	return readl_be(priv->regs + DDR_CSEND_REG) << 24;
 }
 
+static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
+			     unsigned int is_32b, unsigned int banks)
+{
+	rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
+	cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
+	is_32b += 1;
+
+	return 1 << (cols + rows + is_32b + banks);
+}
+
 static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
 {
-	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+	unsigned int cols = 0, rows = 0, is_32b = 0;
 	u32 val;
 
 	val = readl_be(priv->regs + MEMC_CFG_REG);
 	rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 	cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
-	is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
-	banks = 2;
-
-	/* 0 => 11 address bits ... 2 => 13 address bits */
-	rows += 11;
-
-	/* 0 => 8 address bits ... 2 => 10 address bits */
-	cols += 8;
+	is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 
-	return 1 << (cols + rows + (is_32bits + 1) + banks);
+	return bmips_dram_size(cols, rows, is_32b, 2);
 }
 
 static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
-- 
2.1.4

[U-Boot] [PATCH 4/6] dm: cpu: bmips: add BCM6338/BCM6348 support

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 drivers/ram/bmips_ram.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c
index 382e231..ac35fbe 100644
--- a/drivers/ram/bmips_ram.c
+++ b/drivers/ram/bmips_ram.c
@@ -14,6 +14,16 @@
 #include <asm/io.h>
 #include <dm/device.h>
 
+#define SDRAM_CFG_REG		0x0
+#define SDRAM_CFG_COL_SHIFT	4
+#define SDRAM_CFG_COL_MASK	(0x3 << SDRAM_CFG_COL_SHIFT)
+#define SDRAM_CFG_ROW_SHIFT	6
+#define SDRAM_CFG_ROW_MASK	(0x3 << SDRAM_CFG_ROW_SHIFT)
+#define SDRAM_CFG_32B_SHIFT	10
+#define SDRAM_CFG_32B_MASK	(1 << SDRAM_CFG_32B_SHIFT)
+#define SDRAM_CFG_BANK_SHIFT	13
+#define SDRAM_CFG_BANK_MASK	(1 << SDRAM_CFG_BANK_SHIFT)
+
 #define MEMC_CFG_REG		0x4
 #define MEMC_CFG_32B_SHIFT	1
 #define MEMC_CFG_32B_MASK	(1 << MEMC_CFG_32B_SHIFT)
@@ -50,6 +60,20 @@ static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
 	return 1 << (cols + rows + is_32b + banks);
 }
 
+static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
+{
+	unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
+	u32 val;
+
+	val = readl_be(priv->regs + SDRAM_CFG_REG);
+	rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
+	cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
+	is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
+	banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
+
+	return bmips_dram_size(cols, rows, is_32b, banks);
+}
+
 static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
 {
 	unsigned int cols = 0, rows = 0, is_32b = 0;
@@ -82,6 +106,10 @@ static const struct bmips_ram_hw bmips_ram_bcm6328 = {
 	.get_ram_size = bcm6328_get_ram_size,
 };
 
+static const struct bmips_ram_hw bmips_ram_bcm6338 = {
+	.get_ram_size = bcm6338_get_ram_size,
+};
+
 static const struct bmips_ram_hw bmips_ram_bcm6358 = {
 	.get_ram_size = bcm6358_get_ram_size,
 };
@@ -91,6 +119,9 @@ static const struct udevice_id bmips_ram_ids[] = {
 		.compatible = "brcm,bcm6328-mc",
 		.data = (ulong)&bmips_ram_bcm6328,
 	}, {
+		.compatible = "brcm,bcm6338-mc",
+		.data = (ulong)&bmips_ram_bcm6338,
+	}, {
 		.compatible = "brcm,bcm6358-mc",
 		.data = (ulong)&bmips_ram_bcm6358,
 	}, { /* sentinel */ }
-- 
2.1.4

[U-Boot] [PATCH 5/6] MIPS: add support for Broadcom MIPS BCM6348 SoC family

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 arch/mips/dts/brcm,bcm6348.dtsi           | 127 ++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig              |  18 +++++
 arch/mips/mach-bmips/include/ioremap.h    |   3 +-
 include/configs/bmips_bcm6348.h           |  30 +++++++
 include/dt-bindings/clock/bcm6348-clock.h |  22 ++++++
 include/dt-bindings/reset/bcm6348-reset.h |  22 ++++++
 6 files changed, 221 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/brcm,bcm6348.dtsi
 create mode 100644 include/configs/bmips_bcm6348.h
 create mode 100644 include/dt-bindings/clock/bcm6348-clock.h
 create mode 100644 include/dt-bindings/reset/bcm6348-reset.h

diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
new file mode 100644
index 0000000..711b643
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6348-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6348-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm6348";
+
+	cpus {
+		reg = <0xfffe0000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu at 0 {
+			compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_clk: periph-clk {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0xfffe0004 0x4>;
+			#clock-cells = <1>;
+		};
+	};
+
+	pflash: nor at 1fc00000 {
+		compatible = "cfi-flash";
+		reg = <0x1fc00000 0x2000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		status = "disabled";
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		pll_cntl: syscon at fffe0008 {
+			compatible = "syscon";
+			reg = <0xfffe0008 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		periph_rst: reset-controller at fffe0028 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0xfffe0028 0x4>;
+			#reset-cells = <1>;
+		};
+
+		wdt: watchdog at fffe021c {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xfffe021c 0xc>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
+		uart0: serial at fffe0300 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe0300 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		gpio1: gpio-controller at fffe0400 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <5>;
+
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller at fffe0404 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			status = "disabled";
+		};
+
+		memory-controller at fffe2300 {
+			compatible = "brcm,bcm6338-mc";
+			reg = <0xfffe2300 0x38>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 4a0c383..c2b0f89 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -3,6 +3,7 @@ menu "Broadcom MIPS platforms"
 
 config SYS_SOC
 	default "bcm6328" if SOC_BMIPS_BCM6328
+	default "bcm6348" if SOC_BMIPS_BCM6348
 	default "bcm6358" if SOC_BMIPS_BCM6358
 	default "bcm63268" if SOC_BMIPS_BCM63268
 
@@ -20,6 +21,17 @@ config SOC_BMIPS_BCM6328
 	help
 	  This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
 
+config SOC_BMIPS_BCM6348
+	bool "BMIPS BCM6348 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_WATCHDOG
+	help
+	  This supports BMIPS BCM6348 family.
+
 config SOC_BMIPS_BCM6358
 	bool "BMIPS BCM6358 family"
 	select SUPPORTS_BIG_ENDIAN
@@ -53,6 +65,11 @@ config BOARD_COMTREND_AR5387UN
 	depends on SOC_BMIPS_BCM6328
 	select BMIPS_SUPPORTS_BOOT_RAM
 
+config BOARD_COMTREND_CT5361
+	bool "Comtrend CT-5361"
+	depends on SOC_BMIPS_BCM6348
+	select BMIPS_SUPPORTS_BOOT_RAM
+
 config BOARD_COMTREND_VR3032U
 	bool "Comtrend VR-3032u board"
 	depends on SOC_BMIPS_BCM63268
@@ -87,6 +104,7 @@ config BMIPS_SUPPORTS_BOOT_RAM
 	bool
 
 source "board/comtrend/ar5387un/Kconfig"
+source "board/comtrend/ct5361/Kconfig"
 source "board/comtrend/vr3032u/Kconfig"
 source "board/huawei/hg556a/Kconfig"
 source "board/sfr/nb4_ser/Kconfig"
diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h
index 404690e..13842aa 100644
--- a/arch/mips/mach-bmips/include/ioremap.h
+++ b/arch/mips/mach-bmips/include/ioremap.h
@@ -18,7 +18,8 @@ static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
 
 static inline int is_bmips_internal_registers(phys_addr_t offset)
 {
-#if defined(CONFIG_SOC_BMIPS_BCM6358)
+#if defined(CONFIG_SOC_BMIPS_BCM6348) || \
+	defined(CONFIG_SOC_BMIPS_BCM6358)
 	if (offset >= 0xfffe0000)
 		return 1;
 #endif
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
new file mode 100644
index 0000000..e9f53d6
--- /dev/null
+++ b/include/configs/bmips_bcm6348.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6348_H
+#define __CONFIG_BMIPS_BCM6348_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	128000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xbfc00000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6348_H */
diff --git a/include/dt-bindings/clock/bcm6348-clock.h b/include/dt-bindings/clock/bcm6348-clock.h
new file mode 100644
index 0000000..5af066b
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6348-clock.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
+#define __DT_BINDINGS_CLOCK_BCM6348_H
+
+#define BCM6348_CLK_ADSL	0
+#define BCM6348_CLK_MPI		1
+#define BCM6348_CLK_SDRAM	2
+#define BCM6348_CLK_M2M		3
+#define BCM6348_CLK_ENET	4
+#define BCM6348_CLK_SAR		5
+#define BCM6348_CLK_USBS	6
+#define BCM6348_CLK_USBH	8
+#define BCM6348_CLK_SPI		9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */
diff --git a/include/dt-bindings/reset/bcm6348-reset.h b/include/dt-bindings/reset/bcm6348-reset.h
new file mode 100644
index 0000000..173937b
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6348-reset.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6348_H
+#define __DT_BINDINGS_RESET_BCM6348_H
+
+#define BCM6348_RST_SPI		0
+#define BCM6348_RST_ENET	2
+#define BCM6348_RST_USBH	3
+#define BCM6348_RST_USBS	4
+#define BCM6348_RST_ADSL	5
+#define BCM6348_RST_DMAMEM	6
+#define BCM6348_RST_SAR		7
+#define BCM6348_RST_ACLC	8
+#define BCM6348_RST_ADSL_MIPS	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6348_H */
-- 
2.1.4

[U-Boot] [PATCH 6/6] MIPS: add BMIPS Comtrend CT-5361 board

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 arch/mips/dts/Makefile                |  1 +
 arch/mips/dts/comtrend,ct-5361.dts    | 49 ++++++++++++++++++++++++++++++
 board/comtrend/ct5361/Kconfig         | 12 ++++++++
 board/comtrend/ct5361/MAINTAINERS     |  6 ++++
 board/comtrend/ct5361/Makefile        |  5 +++
 board/comtrend/ct5361/ct-5361.c       |  7 +++++
 configs/comtrend_ct5361_ram_defconfig | 57 +++++++++++++++++++++++++++++++++++
 include/configs/comtrend_ct5361.h     | 20 ++++++++++++
 8 files changed, 157 insertions(+)
 create mode 100644 arch/mips/dts/comtrend,ct-5361.dts
 create mode 100644 board/comtrend/ct5361/Kconfig
 create mode 100644 board/comtrend/ct5361/MAINTAINERS
 create mode 100644 board/comtrend/ct5361/Makefile
 create mode 100644 board/comtrend/ct5361/ct-5361.c
 create mode 100644 configs/comtrend_ct5361_ram_defconfig
 create mode 100644 include/configs/comtrend_ct5361.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 4c02c48..9bab744 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
 dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
+dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
 dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
 dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts
new file mode 100644
index 0000000..c909a52
--- /dev/null
+++ b/arch/mips/dts/comtrend,ct-5361.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6348.dtsi"
+
+/ {
+	model = "Comtrend CT-5361";
+	compatible = "comtrend,ct-5361", "brcm,bcm6348";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_green {
+			label = "CT-5361:green:power";
+			gpios = <&gpio0 0 1>;
+		};
+
+		alarm_red {
+			label = "CT-5361:red:alarm";
+			gpios = <&gpio0 2 1>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&pflash {
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
diff --git a/board/comtrend/ct5361/Kconfig b/board/comtrend/ct5361/Kconfig
new file mode 100644
index 0000000..d77d814
--- /dev/null
+++ b/board/comtrend/ct5361/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_CT5361
+
+config SYS_BOARD
+	default "ct5361"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_ct5361"
+
+endif
diff --git a/board/comtrend/ct5361/MAINTAINERS b/board/comtrend/ct5361/MAINTAINERS
new file mode 100644
index 0000000..aea737a
--- /dev/null
+++ b/board/comtrend/ct5361/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND CT-5361 BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/ct-5361/
+F:	include/configs/comtrend_ct5361.h
+F:	configs/comtrend_ct5361_ram_defconfig
diff --git a/board/comtrend/ct5361/Makefile b/board/comtrend/ct5361/Makefile
new file mode 100644
index 0000000..872e80a
--- /dev/null
+++ b/board/comtrend/ct5361/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ct-5361.o
diff --git a/board/comtrend/ct5361/ct-5361.c b/board/comtrend/ct5361/ct-5361.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/comtrend/ct5361/ct-5361.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig
new file mode 100644
index 0000000..9ec0c41
--- /dev/null
+++ b/configs/comtrend_ct5361_ram_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BAUDRATE=115200
+CONFIG_BCM6345_CLK=y
+CONFIG_BCM6345_GPIO=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BMIPS_BOOT_RAM=y
+CONFIG_BOARD_COMTREND_CT5361=y
+CONFIG_CFI_FLASH=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_FLASH=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
+CONFIG_SOC_BMIPS_BCM6348=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_PROMPT="CT-5361 # "
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_WDT=y
+CONFIG_WDT_BCM6345=y
diff --git a/include/configs/comtrend_ct5361.h b/include/configs/comtrend_ct5361.h
new file mode 100644
index 0000000..099684d
--- /dev/null
+++ b/include/configs/comtrend_ct5361.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6348.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
-- 
2.1.4

[U-Boot] [PATCH v2 0/6] mips: bmips: add BCM6348 SoC support

[Álvaro Fernández Rojas]

BCM6348 is one of the first BCM63xx SoCs and prior to BCM6358, which means
that it also needs ioremap "hacks".
Appart from that, rev a1 BCM6348 SoCs have a HW bug and it's pll_conf
register can't be used to perform reboots.

v2: minor fixes.

Álvaro Fernández Rojas (6):
  dm: cpu: bmips: rename cpu_desc specific functions
  dm: cpu: bmips: add BCM6348 support
  dm: ram: bmips: split bcm6358_get_ram_size
  dm: cpu: bmips: add BCM6338/BCM6348 support
  MIPS: add support for Broadcom MIPS BCM6348 SoC family
  MIPS: add BMIPS Comtrend CT-5361 board

 arch/mips/dts/Makefile                    |   1 +
 arch/mips/dts/brcm,bcm6348.dtsi           | 127 ++++++++++++++++++++++++++++++
 arch/mips/dts/comtrend,ct-5361.dts        |  49 ++++++++++++
 arch/mips/mach-bmips/Kconfig              |  18 +++++
 arch/mips/mach-bmips/include/ioremap.h    |   3 +-
 board/comtrend/ct5361/Kconfig             |  12 +++
 board/comtrend/ct5361/MAINTAINERS         |   6 ++
 board/comtrend/ct5361/Makefile            |   5 ++
 board/comtrend/ct5361/ct-5361.c           |   7 ++
 configs/comtrend_ct5361_ram_defconfig     |  57 ++++++++++++++
 drivers/cpu/bmips_cpu.c                   |  44 +++++++++--
 drivers/ram/bmips_ram.c                   |  54 ++++++++++---
 include/configs/bmips_bcm6348.h           |  30 +++++++
 include/configs/comtrend_ct5361.h         |  20 +++++
 include/dt-bindings/clock/bcm6348-clock.h |  22 ++++++
 include/dt-bindings/reset/bcm6348-reset.h |  22 ++++++
 16 files changed, 461 insertions(+), 16 deletions(-)
 create mode 100644 arch/mips/dts/brcm,bcm6348.dtsi
 create mode 100644 arch/mips/dts/comtrend,ct-5361.dts
 create mode 100644 board/comtrend/ct5361/Kconfig
 create mode 100644 board/comtrend/ct5361/MAINTAINERS
 create mode 100644 board/comtrend/ct5361/Makefile
 create mode 100644 board/comtrend/ct5361/ct-5361.c
 create mode 100644 configs/comtrend_ct5361_ram_defconfig
 create mode 100644 include/configs/bmips_bcm6348.h
 create mode 100644 include/configs/comtrend_ct5361.h
 create mode 100644 include/dt-bindings/clock/bcm6348-clock.h
 create mode 100644 include/dt-bindings/reset/bcm6348-reset.h

-- 
2.1.4

[U-Boot] [PATCH v2 1/6] dm: cpu: bmips: rename cpu_desc specific functions

[Álvaro Fernández Rojas]

Use a generic name for cpu_desc functions instead of using a specific SoC one.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 v2: no changes.

 drivers/cpu/bmips_cpu.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 379acf2..6087163 100644
--- a/drivers/cpu/bmips_cpu.c
+++ b/drivers/cpu/bmips_cpu.c
@@ -56,7 +56,7 @@ struct bmips_cpu_priv {
 };
 
 /* Specific CPU Ops */
-static int bcm6358_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
+static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 				int size)
 {
 	unsigned short cpu_id;
@@ -72,7 +72,7 @@ static int bcm6358_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 	return 0;
 }
 
-static int bcm6328_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
+static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 				int size)
 {
 	unsigned int cpu_id;
@@ -166,19 +166,19 @@ static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 }
 
 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
-	.get_cpu_desc = bcm6328_get_cpu_desc,
+	.get_cpu_desc = bmips_long_cpu_desc,
 	.get_cpu_freq = bcm6328_get_cpu_freq,
 	.get_cpu_count = bcm6328_get_cpu_count,
 };
 
 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
-	.get_cpu_desc = bcm6358_get_cpu_desc,
+	.get_cpu_desc = bmips_short_cpu_desc,
 	.get_cpu_freq = bcm6358_get_cpu_freq,
 	.get_cpu_count = bcm6358_get_cpu_count,
 };
 
 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
-	.get_cpu_desc = bcm6328_get_cpu_desc,
+	.get_cpu_desc = bmips_long_cpu_desc,
 	.get_cpu_freq = bcm63268_get_cpu_freq,
 	.get_cpu_count = bcm6358_get_cpu_count,
 };
-- 
2.1.4

[U-Boot] [PATCH v2 2/6] dm: cpu: bmips: add BCM6348 support

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 v2: no changes.

 drivers/cpu/bmips_cpu.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 6087163..2381081 100644
--- a/drivers/cpu/bmips_cpu.c
+++ b/drivers/cpu/bmips_cpu.c
@@ -30,6 +30,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define STRAPBUS_6328_FCVO_SHIFT	7
 #define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
 
+#define REG_BCM6348_PERF_MIPSPLLCFG	0x34
+#define MIPSPLLCFG_6348_M1CPU_SHIFT	6
+#define MIPSPLLCFG_6348_M1CPU_MASK	(0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
+#define MIPSPLLCFG_6348_N2_SHIFT	15
+#define MIPSPLLCFG_6348_N2_MASK		(0x1F << MIPSPLLCFG_6348_N2_SHIFT)
+#define MIPSPLLCFG_6348_N1_SHIFT	20
+#define MIPSPLLCFG_6348_N1_MASK		(0x7 << MIPSPLLCFG_6348_N1_SHIFT)
+
 #define REG_BCM6358_DDR_DMIPSPLLCFG	0x12b8
 #define DMIPSPLLCFG_6358_M1_SHIFT	0
 #define DMIPSPLLCFG_6358_M1_MASK	(0xff << DMIPSPLLCFG_6358_M1_SHIFT)
@@ -115,6 +123,18 @@ static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 	}
 }
 
+static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+	unsigned int tmp, n1, n2, m1;
+
+	tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
+	n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
+	n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
+	m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
+
+	return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
+}
+
 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
 {
 	unsigned int tmp, n1, n2, m1;
@@ -160,6 +180,11 @@ static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
 		return 2;
 }
 
+static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
+{
+	return 1;
+}
+
 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 {
 	return 2;
@@ -171,6 +196,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
 	.get_cpu_count = bcm6328_get_cpu_count,
 };
 
+static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
+	.get_cpu_desc = bmips_short_cpu_desc,
+	.get_cpu_freq = bcm6348_get_cpu_freq,
+	.get_cpu_count = bcm6345_get_cpu_count,
+};
+
 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
 	.get_cpu_desc = bmips_short_cpu_desc,
 	.get_cpu_freq = bcm6358_get_cpu_freq,
@@ -262,6 +293,9 @@ static const struct udevice_id bmips_cpu_ids[] = {
 		.compatible = "brcm,bcm6328-cpu",
 		.data = (ulong)&bmips_cpu_bcm6328,
 	}, {
+		.compatible = "brcm,bcm6348-cpu",
+		.data = (ulong)&bmips_cpu_bcm6348,
+	}, {
 		.compatible = "brcm,bcm6358-cpu",
 		.data = (ulong)&bmips_cpu_bcm6358,
 	}, {
-- 
2.1.4

[U-Boot] [PATCH v2 3/6] dm: ram: bmips: split bcm6358_get_ram_size

[Álvaro Fernández Rojas]

This is done in order to reuse ram size calculation for BCM6338/BCM6348

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 v2: no changes.

 drivers/ram/bmips_ram.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c
index d0f7cd7..382e231 100644
--- a/drivers/ram/bmips_ram.c
+++ b/drivers/ram/bmips_ram.c
@@ -40,24 +40,27 @@ static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
 	return readl_be(priv->regs + DDR_CSEND_REG) << 24;
 }
 
+static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
+			     unsigned int is_32b, unsigned int banks)
+{
+	rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
+	cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
+	is_32b += 1;
+
+	return 1 << (cols + rows + is_32b + banks);
+}
+
 static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
 {
-	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+	unsigned int cols = 0, rows = 0, is_32b = 0;
 	u32 val;
 
 	val = readl_be(priv->regs + MEMC_CFG_REG);
 	rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 	cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
-	is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
-	banks = 2;
-
-	/* 0 => 11 address bits ... 2 => 13 address bits */
-	rows += 11;
-
-	/* 0 => 8 address bits ... 2 => 10 address bits */
-	cols += 8;
+	is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 
-	return 1 << (cols + rows + (is_32bits + 1) + banks);
+	return bmips_dram_size(cols, rows, is_32b, 2);
 }
 
 static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
-- 
2.1.4

[U-Boot] [PATCH v2 4/6] dm: ram: bmips: add BCM6338/BCM6348 support

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 v2: "dm: ram" driver instead of cpu.

 drivers/ram/bmips_ram.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c
index 382e231..ac35fbe 100644
--- a/drivers/ram/bmips_ram.c
+++ b/drivers/ram/bmips_ram.c
@@ -14,6 +14,16 @@
 #include <asm/io.h>
 #include <dm/device.h>
 
+#define SDRAM_CFG_REG		0x0
+#define SDRAM_CFG_COL_SHIFT	4
+#define SDRAM_CFG_COL_MASK	(0x3 << SDRAM_CFG_COL_SHIFT)
+#define SDRAM_CFG_ROW_SHIFT	6
+#define SDRAM_CFG_ROW_MASK	(0x3 << SDRAM_CFG_ROW_SHIFT)
+#define SDRAM_CFG_32B_SHIFT	10
+#define SDRAM_CFG_32B_MASK	(1 << SDRAM_CFG_32B_SHIFT)
+#define SDRAM_CFG_BANK_SHIFT	13
+#define SDRAM_CFG_BANK_MASK	(1 << SDRAM_CFG_BANK_SHIFT)
+
 #define MEMC_CFG_REG		0x4
 #define MEMC_CFG_32B_SHIFT	1
 #define MEMC_CFG_32B_MASK	(1 << MEMC_CFG_32B_SHIFT)
@@ -50,6 +60,20 @@ static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
 	return 1 << (cols + rows + is_32b + banks);
 }
 
+static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
+{
+	unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
+	u32 val;
+
+	val = readl_be(priv->regs + SDRAM_CFG_REG);
+	rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
+	cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
+	is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
+	banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
+
+	return bmips_dram_size(cols, rows, is_32b, banks);
+}
+
 static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
 {
 	unsigned int cols = 0, rows = 0, is_32b = 0;
@@ -82,6 +106,10 @@ static const struct bmips_ram_hw bmips_ram_bcm6328 = {
 	.get_ram_size = bcm6328_get_ram_size,
 };
 
+static const struct bmips_ram_hw bmips_ram_bcm6338 = {
+	.get_ram_size = bcm6338_get_ram_size,
+};
+
 static const struct bmips_ram_hw bmips_ram_bcm6358 = {
 	.get_ram_size = bcm6358_get_ram_size,
 };
@@ -91,6 +119,9 @@ static const struct udevice_id bmips_ram_ids[] = {
 		.compatible = "brcm,bcm6328-mc",
 		.data = (ulong)&bmips_ram_bcm6328,
 	}, {
+		.compatible = "brcm,bcm6338-mc",
+		.data = (ulong)&bmips_ram_bcm6338,
+	}, {
 		.compatible = "brcm,bcm6358-mc",
 		.data = (ulong)&bmips_ram_bcm6358,
 	}, { /* sentinel */ }
-- 
2.1.4

[U-Boot] [PATCH v2 5/6] MIPS: add support for Broadcom MIPS BCM6348 SoC family

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 v2: remove comtrend ct-5361 Kconfig

 arch/mips/dts/brcm,bcm6348.dtsi           | 127 ++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig              |  12 +++
 arch/mips/mach-bmips/include/ioremap.h    |   3 +-
 include/configs/bmips_bcm6348.h           |  30 +++++++
 include/dt-bindings/clock/bcm6348-clock.h |  22 ++++++
 include/dt-bindings/reset/bcm6348-reset.h |  22 ++++++
 6 files changed, 215 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/brcm,bcm6348.dtsi
 create mode 100644 include/configs/bmips_bcm6348.h
 create mode 100644 include/dt-bindings/clock/bcm6348-clock.h
 create mode 100644 include/dt-bindings/reset/bcm6348-reset.h

diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
new file mode 100644
index 0000000..711b643
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6348-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6348-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm6348";
+
+	cpus {
+		reg = <0xfffe0000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu at 0 {
+			compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_clk: periph-clk {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0xfffe0004 0x4>;
+			#clock-cells = <1>;
+		};
+	};
+
+	pflash: nor at 1fc00000 {
+		compatible = "cfi-flash";
+		reg = <0x1fc00000 0x2000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		status = "disabled";
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		pll_cntl: syscon at fffe0008 {
+			compatible = "syscon";
+			reg = <0xfffe0008 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		periph_rst: reset-controller at fffe0028 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0xfffe0028 0x4>;
+			#reset-cells = <1>;
+		};
+
+		wdt: watchdog at fffe021c {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xfffe021c 0xc>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
+		uart0: serial at fffe0300 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe0300 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		gpio1: gpio-controller at fffe0400 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <5>;
+
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller at fffe0404 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			status = "disabled";
+		};
+
+		memory-controller at fffe2300 {
+			compatible = "brcm,bcm6338-mc";
+			reg = <0xfffe2300 0x38>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 4a0c383..b7f7b1e 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -3,6 +3,7 @@ menu "Broadcom MIPS platforms"
 
 config SYS_SOC
 	default "bcm6328" if SOC_BMIPS_BCM6328
+	default "bcm6348" if SOC_BMIPS_BCM6348
 	default "bcm6358" if SOC_BMIPS_BCM6358
 	default "bcm63268" if SOC_BMIPS_BCM63268
 
@@ -20,6 +21,17 @@ config SOC_BMIPS_BCM6328
 	help
 	  This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
 
+config SOC_BMIPS_BCM6348
+	bool "BMIPS BCM6348 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_WATCHDOG
+	help
+	  This supports BMIPS BCM6348 family.
+
 config SOC_BMIPS_BCM6358
 	bool "BMIPS BCM6358 family"
 	select SUPPORTS_BIG_ENDIAN
diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h
index 404690e..d3dc0b8 100644
--- a/arch/mips/mach-bmips/include/ioremap.h
+++ b/arch/mips/mach-bmips/include/ioremap.h
@@ -18,7 +18,8 @@ static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
 
 static inline int is_bmips_internal_registers(phys_addr_t offset)
 {
-#if defined(CONFIG_SOC_BMIPS_BCM6358)
+#if defined(CONFIG_SOC_BMIPS_BCM6348) || \
+	defined(CONFIG_SOC_BMIPS_BCM6358)
 	if (offset >= 0xfffe0000)
 		return 1;
 #endif
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
new file mode 100644
index 0000000..e9f53d6
--- /dev/null
+++ b/include/configs/bmips_bcm6348.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6348_H
+#define __CONFIG_BMIPS_BCM6348_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	128000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xbfc00000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6348_H */
diff --git a/include/dt-bindings/clock/bcm6348-clock.h b/include/dt-bindings/clock/bcm6348-clock.h
new file mode 100644
index 0000000..5af066b
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6348-clock.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
+#define __DT_BINDINGS_CLOCK_BCM6348_H
+
+#define BCM6348_CLK_ADSL	0
+#define BCM6348_CLK_MPI		1
+#define BCM6348_CLK_SDRAM	2
+#define BCM6348_CLK_M2M		3
+#define BCM6348_CLK_ENET	4
+#define BCM6348_CLK_SAR		5
+#define BCM6348_CLK_USBS	6
+#define BCM6348_CLK_USBH	8
+#define BCM6348_CLK_SPI		9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */
diff --git a/include/dt-bindings/reset/bcm6348-reset.h b/include/dt-bindings/reset/bcm6348-reset.h
new file mode 100644
index 0000000..173937b
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6348-reset.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6348_H
+#define __DT_BINDINGS_RESET_BCM6348_H
+
+#define BCM6348_RST_SPI		0
+#define BCM6348_RST_ENET	2
+#define BCM6348_RST_USBH	3
+#define BCM6348_RST_USBS	4
+#define BCM6348_RST_ADSL	5
+#define BCM6348_RST_DMAMEM	6
+#define BCM6348_RST_SAR		7
+#define BCM6348_RST_ACLC	8
+#define BCM6348_RST_ADSL_MIPS	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6348_H */
-- 
2.1.4

[U-Boot] [PATCH v2 6/6] MIPS: add BMIPS Comtrend CT-5361 board

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 v2: add comtrend ct-5361 Kconfig

 arch/mips/dts/Makefile                |  1 +
 arch/mips/dts/comtrend,ct-5361.dts    | 49 ++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig          |  6 ++++
 board/comtrend/ct5361/Kconfig         | 12 ++++++++
 board/comtrend/ct5361/MAINTAINERS     |  6 ++++
 board/comtrend/ct5361/Makefile        |  5 +++
 board/comtrend/ct5361/ct-5361.c       |  7 +++++
 configs/comtrend_ct5361_ram_defconfig | 57 +++++++++++++++++++++++++++++++++++
 include/configs/comtrend_ct5361.h     | 20 ++++++++++++
 9 files changed, 163 insertions(+)
 create mode 100644 arch/mips/dts/comtrend,ct-5361.dts
 create mode 100644 board/comtrend/ct5361/Kconfig
 create mode 100644 board/comtrend/ct5361/MAINTAINERS
 create mode 100644 board/comtrend/ct5361/Makefile
 create mode 100644 board/comtrend/ct5361/ct-5361.c
 create mode 100644 configs/comtrend_ct5361_ram_defconfig
 create mode 100644 include/configs/comtrend_ct5361.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 4c02c48..9bab744 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
 dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
+dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
 dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
 dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts
new file mode 100644
index 0000000..c909a52
--- /dev/null
+++ b/arch/mips/dts/comtrend,ct-5361.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6348.dtsi"
+
+/ {
+	model = "Comtrend CT-5361";
+	compatible = "comtrend,ct-5361", "brcm,bcm6348";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_green {
+			label = "CT-5361:green:power";
+			gpios = <&gpio0 0 1>;
+		};
+
+		alarm_red {
+			label = "CT-5361:red:alarm";
+			gpios = <&gpio0 2 1>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&pflash {
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index b7f7b1e..c2b0f89 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -65,6 +65,11 @@ config BOARD_COMTREND_AR5387UN
 	depends on SOC_BMIPS_BCM6328
 	select BMIPS_SUPPORTS_BOOT_RAM
 
+config BOARD_COMTREND_CT5361
+	bool "Comtrend CT-5361"
+	depends on SOC_BMIPS_BCM6348
+	select BMIPS_SUPPORTS_BOOT_RAM
+
 config BOARD_COMTREND_VR3032U
 	bool "Comtrend VR-3032u board"
 	depends on SOC_BMIPS_BCM63268
@@ -99,6 +104,7 @@ config BMIPS_SUPPORTS_BOOT_RAM
 	bool
 
 source "board/comtrend/ar5387un/Kconfig"
+source "board/comtrend/ct5361/Kconfig"
 source "board/comtrend/vr3032u/Kconfig"
 source "board/huawei/hg556a/Kconfig"
 source "board/sfr/nb4_ser/Kconfig"
diff --git a/board/comtrend/ct5361/Kconfig b/board/comtrend/ct5361/Kconfig
new file mode 100644
index 0000000..d77d814
--- /dev/null
+++ b/board/comtrend/ct5361/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_CT5361
+
+config SYS_BOARD
+	default "ct5361"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_ct5361"
+
+endif
diff --git a/board/comtrend/ct5361/MAINTAINERS b/board/comtrend/ct5361/MAINTAINERS
new file mode 100644
index 0000000..aea737a
--- /dev/null
+++ b/board/comtrend/ct5361/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND CT-5361 BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/ct-5361/
+F:	include/configs/comtrend_ct5361.h
+F:	configs/comtrend_ct5361_ram_defconfig
diff --git a/board/comtrend/ct5361/Makefile b/board/comtrend/ct5361/Makefile
new file mode 100644
index 0000000..872e80a
--- /dev/null
+++ b/board/comtrend/ct5361/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ct-5361.o
diff --git a/board/comtrend/ct5361/ct-5361.c b/board/comtrend/ct5361/ct-5361.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/comtrend/ct5361/ct-5361.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig
new file mode 100644
index 0000000..9ec0c41
--- /dev/null
+++ b/configs/comtrend_ct5361_ram_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BAUDRATE=115200
+CONFIG_BCM6345_CLK=y
+CONFIG_BCM6345_GPIO=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BMIPS_BOOT_RAM=y
+CONFIG_BOARD_COMTREND_CT5361=y
+CONFIG_CFI_FLASH=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_FLASH=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
+CONFIG_SOC_BMIPS_BCM6348=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_PROMPT="CT-5361 # "
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_WDT=y
+CONFIG_WDT_BCM6345=y
diff --git a/include/configs/comtrend_ct5361.h b/include/configs/comtrend_ct5361.h
new file mode 100644
index 0000000..099684d
--- /dev/null
+++ b/include/configs/comtrend_ct5361.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6348.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
-- 
2.1.4

[U-Boot] [PATCH 1/6] dm: cpu: bmips: rename cpu_desc specific functions

[Simon Glass]

On 12 May 2017 at 17:23, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> Use a generic name for cpu_desc functions instead of using a specific SoC one.
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  drivers/cpu/bmips_cpu.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 2/6] dm: cpu: bmips: add BCM6348 support

[Simon Glass]

On 15 May 2017 at 11:13, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  v2: no changes.
>
>  drivers/cpu/bmips_cpu.c | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 3/6] dm: ram: bmips: split bcm6358_get_ram_size

[Simon Glass]

On 15 May 2017 at 11:13, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> This is done in order to reuse ram size calculation for BCM6338/BCM6348
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  v2: no changes.
>
>  drivers/ram/bmips_ram.c | 23 +++++++++++++----------
>  1 file changed, 13 insertions(+), 10 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 4/6] dm: cpu: bmips: add BCM6338/BCM6348 support

[Simon Glass]

On 12 May 2017 at 17:23, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  drivers/ram/bmips_ram.c | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 5/6] MIPS: add support for Broadcom MIPS BCM6348 SoC family

[Simon Glass]

On 15 May 2017 at 11:13, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  v2: remove comtrend ct-5361 Kconfig
>
>  arch/mips/dts/brcm,bcm6348.dtsi           | 127 ++++++++++++++++++++++++++++++
>  arch/mips/mach-bmips/Kconfig              |  12 +++
>  arch/mips/mach-bmips/include/ioremap.h    |   3 +-
>  include/configs/bmips_bcm6348.h           |  30 +++++++
>  include/dt-bindings/clock/bcm6348-clock.h |  22 ++++++
>  include/dt-bindings/reset/bcm6348-reset.h |  22 ++++++
>  6 files changed, 215 insertions(+), 1 deletion(-)
>  create mode 100644 arch/mips/dts/brcm,bcm6348.dtsi
>  create mode 100644 include/configs/bmips_bcm6348.h
>  create mode 100644 include/dt-bindings/clock/bcm6348-clock.h
>  create mode 100644 include/dt-bindings/reset/bcm6348-reset.h
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 6/6] MIPS: add BMIPS Comtrend CT-5361 board

[Simon Glass]

On 15 May 2017 at 11:13, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  v2: add comtrend ct-5361 Kconfig
>
>  arch/mips/dts/Makefile                |  1 +
>  arch/mips/dts/comtrend,ct-5361.dts    | 49 ++++++++++++++++++++++++++++++
>  arch/mips/mach-bmips/Kconfig          |  6 ++++
>  board/comtrend/ct5361/Kconfig         | 12 ++++++++
>  board/comtrend/ct5361/MAINTAINERS     |  6 ++++
>  board/comtrend/ct5361/Makefile        |  5 +++
>  board/comtrend/ct5361/ct-5361.c       |  7 +++++
>  configs/comtrend_ct5361_ram_defconfig | 57 +++++++++++++++++++++++++++++++++++
>  include/configs/comtrend_ct5361.h     | 20 ++++++++++++
>  9 files changed, 163 insertions(+)
>  create mode 100644 arch/mips/dts/comtrend,ct-5361.dts
>  create mode 100644 board/comtrend/ct5361/Kconfig
>  create mode 100644 board/comtrend/ct5361/MAINTAINERS
>  create mode 100644 board/comtrend/ct5361/Makefile
>  create mode 100644 board/comtrend/ct5361/ct-5361.c
>  create mode 100644 configs/comtrend_ct5361_ram_defconfig
>  create mode 100644 include/configs/comtrend_ct5361.h

Reviewed-by: Simon Glass <sjg@chromium.org>

Please see below.

>
> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> index 4c02c48..9bab744 100644
> --- a/arch/mips/dts/Makefile
> +++ b/arch/mips/dts/Makefile
> @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
>  dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
>  dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
>  dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
> +dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
>  dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
>  dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
>  dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
> diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts
> new file mode 100644
> index 0000000..c909a52
> --- /dev/null
> +++ b/arch/mips/dts/comtrend,ct-5361.dts
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +/dts-v1/;
> +
> +#include "brcm,bcm6348.dtsi"
> +
> +/ {
> +       model = "Comtrend CT-5361";
> +       compatible = "comtrend,ct-5361", "brcm,bcm6348";
> +
> +       aliases {
> +               serial0 = &uart0;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };
> +
> +       gpio-leds {
> +               compatible = "gpio-leds";
> +
> +               power_green {
> +                       label = "CT-5361:green:power";
> +                       gpios = <&gpio0 0 1>;
> +               };
> +
> +               alarm_red {
> +                       label = "CT-5361:red:alarm";
> +                       gpios = <&gpio0 2 1>;
> +               };
> +       };
> +};
> +
> +&gpio0 {
> +       status = "okay";
> +};
> +
> +&pflash {
> +       status = "okay";
> +};
> +
> +&uart0 {
> +       u-boot,dm-pre-reloc;
> +       status = "okay";
> +};
> diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
> index b7f7b1e..c2b0f89 100644
> --- a/arch/mips/mach-bmips/Kconfig
> +++ b/arch/mips/mach-bmips/Kconfig
> @@ -65,6 +65,11 @@ config BOARD_COMTREND_AR5387UN
>         depends on SOC_BMIPS_BCM6328
>         select BMIPS_SUPPORTS_BOOT_RAM
>
> +config BOARD_COMTREND_CT5361
> +       bool "Comtrend CT-5361"
> +       depends on SOC_BMIPS_BCM6348
> +       select BMIPS_SUPPORTS_BOOT_RAM

It would be good to add a paragraph describing each of these boards,
peripherals, etc.

[U-Boot] [PATCH v3 0/6] mips: bmips: add BCM6348 SoC support*

[Álvaro Fernández Rojas]

BCM6348 is one of the first BCM63xx SoCs and prior to BCM6358, which means
that it also needs ioremap "hacks".
Appart from that, rev a1 BCM6348 SoCs have a HW bug and it's pll_conf
register can't be used to perform reboots.

v3: introduce changes requested by Simon Glass.
v2: minor fixes.

Álvaro Fernández Rojas (6):
  dm: cpu: bmips: rename cpu_desc specific functions
  dm: cpu: bmips: add BCM6348 support
  dm: ram: bmips: split bcm6358_get_ram_size
  dm: ram: bmips: add BCM6338/BCM6348 support
  MIPS: add support for Broadcom MIPS BCM6348 SoC family
  MIPS: add BMIPS Comtrend CT-5361 board

 arch/mips/dts/Makefile                    |   1 +
 arch/mips/dts/brcm,bcm6348.dtsi           | 127 ++++++++++++++++++++++++++++++
 arch/mips/dts/comtrend,ct-5361.dts        |  49 ++++++++++++
 arch/mips/mach-bmips/Kconfig              |  24 ++++++
 arch/mips/mach-bmips/include/ioremap.h    |   3 +-
 board/comtrend/ct5361/Kconfig             |  12 +++
 board/comtrend/ct5361/MAINTAINERS         |   6 ++
 board/comtrend/ct5361/Makefile            |   5 ++
 board/comtrend/ct5361/ct-5361.c           |   7 ++
 configs/comtrend_ct5361_ram_defconfig     |  57 ++++++++++++++
 drivers/cpu/bmips_cpu.c                   |  44 +++++++++--
 drivers/ram/bmips_ram.c                   |  54 ++++++++++---
 include/configs/bmips_bcm6348.h           |  30 +++++++
 include/configs/comtrend_ct5361.h         |  20 +++++
 include/dt-bindings/clock/bcm6348-clock.h |  22 ++++++
 include/dt-bindings/reset/bcm6348-reset.h |  22 ++++++
 16 files changed, 467 insertions(+), 16 deletions(-)
 create mode 100644 arch/mips/dts/brcm,bcm6348.dtsi
 create mode 100644 arch/mips/dts/comtrend,ct-5361.dts
 create mode 100644 board/comtrend/ct5361/Kconfig
 create mode 100644 board/comtrend/ct5361/MAINTAINERS
 create mode 100644 board/comtrend/ct5361/Makefile
 create mode 100644 board/comtrend/ct5361/ct-5361.c
 create mode 100644 configs/comtrend_ct5361_ram_defconfig
 create mode 100644 include/configs/bmips_bcm6348.h
 create mode 100644 include/configs/comtrend_ct5361.h
 create mode 100644 include/dt-bindings/clock/bcm6348-clock.h
 create mode 100644 include/dt-bindings/reset/bcm6348-reset.h

-- 
2.1.4

[U-Boot] [PATCH v3 1/6] dm: cpu: bmips: rename cpu_desc specific functions

[Álvaro Fernández Rojas]

Use a generic name for cpu_desc functions instead of using a specific SoC one.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 v3: no changes.
 v2: no changes.

 drivers/cpu/bmips_cpu.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 379acf2..6087163 100644
--- a/drivers/cpu/bmips_cpu.c
+++ b/drivers/cpu/bmips_cpu.c
@@ -56,7 +56,7 @@ struct bmips_cpu_priv {
 };
 
 /* Specific CPU Ops */
-static int bcm6358_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
+static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 				int size)
 {
 	unsigned short cpu_id;
@@ -72,7 +72,7 @@ static int bcm6358_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 	return 0;
 }
 
-static int bcm6328_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
+static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 				int size)
 {
 	unsigned int cpu_id;
@@ -166,19 +166,19 @@ static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 }
 
 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
-	.get_cpu_desc = bcm6328_get_cpu_desc,
+	.get_cpu_desc = bmips_long_cpu_desc,
 	.get_cpu_freq = bcm6328_get_cpu_freq,
 	.get_cpu_count = bcm6328_get_cpu_count,
 };
 
 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
-	.get_cpu_desc = bcm6358_get_cpu_desc,
+	.get_cpu_desc = bmips_short_cpu_desc,
 	.get_cpu_freq = bcm6358_get_cpu_freq,
 	.get_cpu_count = bcm6358_get_cpu_count,
 };
 
 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
-	.get_cpu_desc = bcm6328_get_cpu_desc,
+	.get_cpu_desc = bmips_long_cpu_desc,
 	.get_cpu_freq = bcm63268_get_cpu_freq,
 	.get_cpu_count = bcm6358_get_cpu_count,
 };
-- 
2.1.4

[U-Boot] [PATCH v3 2/6] dm: cpu: bmips: add BCM6348 support

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 v3: no changes.
 v2: no changes.

 drivers/cpu/bmips_cpu.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 6087163..2381081 100644
--- a/drivers/cpu/bmips_cpu.c
+++ b/drivers/cpu/bmips_cpu.c
@@ -30,6 +30,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define STRAPBUS_6328_FCVO_SHIFT	7
 #define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
 
+#define REG_BCM6348_PERF_MIPSPLLCFG	0x34
+#define MIPSPLLCFG_6348_M1CPU_SHIFT	6
+#define MIPSPLLCFG_6348_M1CPU_MASK	(0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
+#define MIPSPLLCFG_6348_N2_SHIFT	15
+#define MIPSPLLCFG_6348_N2_MASK		(0x1F << MIPSPLLCFG_6348_N2_SHIFT)
+#define MIPSPLLCFG_6348_N1_SHIFT	20
+#define MIPSPLLCFG_6348_N1_MASK		(0x7 << MIPSPLLCFG_6348_N1_SHIFT)
+
 #define REG_BCM6358_DDR_DMIPSPLLCFG	0x12b8
 #define DMIPSPLLCFG_6358_M1_SHIFT	0
 #define DMIPSPLLCFG_6358_M1_MASK	(0xff << DMIPSPLLCFG_6358_M1_SHIFT)
@@ -115,6 +123,18 @@ static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 	}
 }
 
+static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+	unsigned int tmp, n1, n2, m1;
+
+	tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
+	n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
+	n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
+	m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
+
+	return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
+}
+
 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
 {
 	unsigned int tmp, n1, n2, m1;
@@ -160,6 +180,11 @@ static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
 		return 2;
 }
 
+static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
+{
+	return 1;
+}
+
 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 {
 	return 2;
@@ -171,6 +196,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
 	.get_cpu_count = bcm6328_get_cpu_count,
 };
 
+static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
+	.get_cpu_desc = bmips_short_cpu_desc,
+	.get_cpu_freq = bcm6348_get_cpu_freq,
+	.get_cpu_count = bcm6345_get_cpu_count,
+};
+
 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
 	.get_cpu_desc = bmips_short_cpu_desc,
 	.get_cpu_freq = bcm6358_get_cpu_freq,
@@ -262,6 +293,9 @@ static const struct udevice_id bmips_cpu_ids[] = {
 		.compatible = "brcm,bcm6328-cpu",
 		.data = (ulong)&bmips_cpu_bcm6328,
 	}, {
+		.compatible = "brcm,bcm6348-cpu",
+		.data = (ulong)&bmips_cpu_bcm6348,
+	}, {
 		.compatible = "brcm,bcm6358-cpu",
 		.data = (ulong)&bmips_cpu_bcm6358,
 	}, {
-- 
2.1.4

[U-Boot] [PATCH v3 3/6] dm: ram: bmips: split bcm6358_get_ram_size

[Álvaro Fernández Rojas]

This is done in order to reuse ram size calculation for BCM6338/BCM6348

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 v3: no changes.
 v2: no changes.

 drivers/ram/bmips_ram.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c
index d0f7cd7..382e231 100644
--- a/drivers/ram/bmips_ram.c
+++ b/drivers/ram/bmips_ram.c
@@ -40,24 +40,27 @@ static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
 	return readl_be(priv->regs + DDR_CSEND_REG) << 24;
 }
 
+static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
+			     unsigned int is_32b, unsigned int banks)
+{
+	rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
+	cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
+	is_32b += 1;
+
+	return 1 << (cols + rows + is_32b + banks);
+}
+
 static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
 {
-	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+	unsigned int cols = 0, rows = 0, is_32b = 0;
 	u32 val;
 
 	val = readl_be(priv->regs + MEMC_CFG_REG);
 	rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 	cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
-	is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
-	banks = 2;
-
-	/* 0 => 11 address bits ... 2 => 13 address bits */
-	rows += 11;
-
-	/* 0 => 8 address bits ... 2 => 10 address bits */
-	cols += 8;
+	is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 
-	return 1 << (cols + rows + (is_32bits + 1) + banks);
+	return bmips_dram_size(cols, rows, is_32b, 2);
 }
 
 static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
-- 
2.1.4

[U-Boot] [PATCH v3 4/6] dm: ram: bmips: add BCM6338/BCM6348 support

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 v3: no changes.
 v2: "dm: ram" driver instead of cpu.

 drivers/ram/bmips_ram.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c
index 382e231..ac35fbe 100644
--- a/drivers/ram/bmips_ram.c
+++ b/drivers/ram/bmips_ram.c
@@ -14,6 +14,16 @@
 #include <asm/io.h>
 #include <dm/device.h>
 
+#define SDRAM_CFG_REG		0x0
+#define SDRAM_CFG_COL_SHIFT	4
+#define SDRAM_CFG_COL_MASK	(0x3 << SDRAM_CFG_COL_SHIFT)
+#define SDRAM_CFG_ROW_SHIFT	6
+#define SDRAM_CFG_ROW_MASK	(0x3 << SDRAM_CFG_ROW_SHIFT)
+#define SDRAM_CFG_32B_SHIFT	10
+#define SDRAM_CFG_32B_MASK	(1 << SDRAM_CFG_32B_SHIFT)
+#define SDRAM_CFG_BANK_SHIFT	13
+#define SDRAM_CFG_BANK_MASK	(1 << SDRAM_CFG_BANK_SHIFT)
+
 #define MEMC_CFG_REG		0x4
 #define MEMC_CFG_32B_SHIFT	1
 #define MEMC_CFG_32B_MASK	(1 << MEMC_CFG_32B_SHIFT)
@@ -50,6 +60,20 @@ static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
 	return 1 << (cols + rows + is_32b + banks);
 }
 
+static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
+{
+	unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
+	u32 val;
+
+	val = readl_be(priv->regs + SDRAM_CFG_REG);
+	rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
+	cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
+	is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
+	banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
+
+	return bmips_dram_size(cols, rows, is_32b, banks);
+}
+
 static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
 {
 	unsigned int cols = 0, rows = 0, is_32b = 0;
@@ -82,6 +106,10 @@ static const struct bmips_ram_hw bmips_ram_bcm6328 = {
 	.get_ram_size = bcm6328_get_ram_size,
 };
 
+static const struct bmips_ram_hw bmips_ram_bcm6338 = {
+	.get_ram_size = bcm6338_get_ram_size,
+};
+
 static const struct bmips_ram_hw bmips_ram_bcm6358 = {
 	.get_ram_size = bcm6358_get_ram_size,
 };
@@ -91,6 +119,9 @@ static const struct udevice_id bmips_ram_ids[] = {
 		.compatible = "brcm,bcm6328-mc",
 		.data = (ulong)&bmips_ram_bcm6328,
 	}, {
+		.compatible = "brcm,bcm6338-mc",
+		.data = (ulong)&bmips_ram_bcm6338,
+	}, {
 		.compatible = "brcm,bcm6358-mc",
 		.data = (ulong)&bmips_ram_bcm6358,
 	}, { /* sentinel */ }
-- 
2.1.4

[U-Boot] [PATCH v3 5/6] MIPS: add support for Broadcom MIPS BCM6348 SoC family

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 arch/mips/dts/brcm,bcm6348.dtsi           | 127 ++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig              |  12 +++
 arch/mips/mach-bmips/include/ioremap.h    |   3 +-
 include/configs/bmips_bcm6348.h           |  30 +++++++
 include/dt-bindings/clock/bcm6348-clock.h |  22 ++++++
 include/dt-bindings/reset/bcm6348-reset.h |  22 ++++++
 6 files changed, 215 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/brcm,bcm6348.dtsi
 create mode 100644 include/configs/bmips_bcm6348.h
 create mode 100644 include/dt-bindings/clock/bcm6348-clock.h
 create mode 100644 include/dt-bindings/reset/bcm6348-reset.h

diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
new file mode 100644
index 0000000..711b643
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6348-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6348-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm6348";
+
+	cpus {
+		reg = <0xfffe0000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu at 0 {
+			compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_clk: periph-clk {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0xfffe0004 0x4>;
+			#clock-cells = <1>;
+		};
+	};
+
+	pflash: nor at 1fc00000 {
+		compatible = "cfi-flash";
+		reg = <0x1fc00000 0x2000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		status = "disabled";
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		pll_cntl: syscon at fffe0008 {
+			compatible = "syscon";
+			reg = <0xfffe0008 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		periph_rst: reset-controller at fffe0028 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0xfffe0028 0x4>;
+			#reset-cells = <1>;
+		};
+
+		wdt: watchdog at fffe021c {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xfffe021c 0xc>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
+		uart0: serial at fffe0300 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe0300 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		gpio1: gpio-controller at fffe0400 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <5>;
+
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller at fffe0404 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			status = "disabled";
+		};
+
+		memory-controller at fffe2300 {
+			compatible = "brcm,bcm6338-mc";
+			reg = <0xfffe2300 0x38>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 4a0c383..b7f7b1e 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -3,6 +3,7 @@ menu "Broadcom MIPS platforms"
 
 config SYS_SOC
 	default "bcm6328" if SOC_BMIPS_BCM6328
+	default "bcm6348" if SOC_BMIPS_BCM6348
 	default "bcm6358" if SOC_BMIPS_BCM6358
 	default "bcm63268" if SOC_BMIPS_BCM63268
 
@@ -20,6 +21,17 @@ config SOC_BMIPS_BCM6328
 	help
 	  This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
 
+config SOC_BMIPS_BCM6348
+	bool "BMIPS BCM6348 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_WATCHDOG
+	help
+	  This supports BMIPS BCM6348 family.
+
 config SOC_BMIPS_BCM6358
 	bool "BMIPS BCM6358 family"
 	select SUPPORTS_BIG_ENDIAN
diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h
index 404690e..d3dc0b8 100644
--- a/arch/mips/mach-bmips/include/ioremap.h
+++ b/arch/mips/mach-bmips/include/ioremap.h
@@ -18,7 +18,8 @@ static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
 
 static inline int is_bmips_internal_registers(phys_addr_t offset)
 {
-#if defined(CONFIG_SOC_BMIPS_BCM6358)
+#if defined(CONFIG_SOC_BMIPS_BCM6348) || \
+	defined(CONFIG_SOC_BMIPS_BCM6358)
 	if (offset >= 0xfffe0000)
 		return 1;
 #endif
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
new file mode 100644
index 0000000..e9f53d6
--- /dev/null
+++ b/include/configs/bmips_bcm6348.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6348_H
+#define __CONFIG_BMIPS_BCM6348_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	128000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xbfc00000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6348_H */
diff --git a/include/dt-bindings/clock/bcm6348-clock.h b/include/dt-bindings/clock/bcm6348-clock.h
new file mode 100644
index 0000000..5af066b
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6348-clock.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
+#define __DT_BINDINGS_CLOCK_BCM6348_H
+
+#define BCM6348_CLK_ADSL	0
+#define BCM6348_CLK_MPI		1
+#define BCM6348_CLK_SDRAM	2
+#define BCM6348_CLK_M2M		3
+#define BCM6348_CLK_ENET	4
+#define BCM6348_CLK_SAR		5
+#define BCM6348_CLK_USBS	6
+#define BCM6348_CLK_USBH	8
+#define BCM6348_CLK_SPI		9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */
diff --git a/include/dt-bindings/reset/bcm6348-reset.h b/include/dt-bindings/reset/bcm6348-reset.h
new file mode 100644
index 0000000..173937b
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6348-reset.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6348_H
+#define __DT_BINDINGS_RESET_BCM6348_H
+
+#define BCM6348_RST_SPI		0
+#define BCM6348_RST_ENET	2
+#define BCM6348_RST_USBH	3
+#define BCM6348_RST_USBS	4
+#define BCM6348_RST_ADSL	5
+#define BCM6348_RST_DMAMEM	6
+#define BCM6348_RST_SAR		7
+#define BCM6348_RST_ACLC	8
+#define BCM6348_RST_ADSL_MIPS	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6348_H */
-- 
2.1.4

[U-Boot] [PATCH v3 6/6] MIPS: add BMIPS Comtrend CT-5361 board

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 v3: introduce changes requested by Simon Glass:
  - Add board description.
 v2: add comtrend ct-5361 Kconfig

 arch/mips/dts/Makefile                |  1 +
 arch/mips/dts/comtrend,ct-5361.dts    | 49 ++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig          | 12 ++++++++
 board/comtrend/ct5361/Kconfig         | 12 ++++++++
 board/comtrend/ct5361/MAINTAINERS     |  6 ++++
 board/comtrend/ct5361/Makefile        |  5 +++
 board/comtrend/ct5361/ct-5361.c       |  7 +++++
 configs/comtrend_ct5361_ram_defconfig | 57 +++++++++++++++++++++++++++++++++++
 include/configs/comtrend_ct5361.h     | 20 ++++++++++++
 9 files changed, 169 insertions(+)
 create mode 100644 arch/mips/dts/comtrend,ct-5361.dts
 create mode 100644 board/comtrend/ct5361/Kconfig
 create mode 100644 board/comtrend/ct5361/MAINTAINERS
 create mode 100644 board/comtrend/ct5361/Makefile
 create mode 100644 board/comtrend/ct5361/ct-5361.c
 create mode 100644 configs/comtrend_ct5361_ram_defconfig
 create mode 100644 include/configs/comtrend_ct5361.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 4c02c48..9bab744 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
 dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
+dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
 dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
 dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts
new file mode 100644
index 0000000..c909a52
--- /dev/null
+++ b/arch/mips/dts/comtrend,ct-5361.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6348.dtsi"
+
+/ {
+	model = "Comtrend CT-5361";
+	compatible = "comtrend,ct-5361", "brcm,bcm6348";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_green {
+			label = "CT-5361:green:power";
+			gpios = <&gpio0 0 1>;
+		};
+
+		alarm_red {
+			label = "CT-5361:red:alarm";
+			gpios = <&gpio0 2 1>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&pflash {
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index b7f7b1e..b980587 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -65,6 +65,17 @@ config BOARD_COMTREND_AR5387UN
 	depends on SOC_BMIPS_BCM6328
 	select BMIPS_SUPPORTS_BOOT_RAM
 
+config BOARD_COMTREND_CT5361
+	bool "Comtrend CT-5361"
+	depends on SOC_BMIPS_BCM6348
+	select BMIPS_SUPPORTS_BOOT_RAM
+	help
+	  Comtrend CT-5361 boards have a BCM6348 SoC with 16 MB of RAM and 4 MB
+	  of flash (CFI).
+	  Between its different peripherals there's a BCM5325 switch with 4
+	  ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and a
+	  BCM4312 (miniPCI).
+
 config BOARD_COMTREND_VR3032U
 	bool "Comtrend VR-3032u board"
 	depends on SOC_BMIPS_BCM63268
@@ -99,6 +110,7 @@ config BMIPS_SUPPORTS_BOOT_RAM
 	bool
 
 source "board/comtrend/ar5387un/Kconfig"
+source "board/comtrend/ct5361/Kconfig"
 source "board/comtrend/vr3032u/Kconfig"
 source "board/huawei/hg556a/Kconfig"
 source "board/sfr/nb4_ser/Kconfig"
diff --git a/board/comtrend/ct5361/Kconfig b/board/comtrend/ct5361/Kconfig
new file mode 100644
index 0000000..d77d814
--- /dev/null
+++ b/board/comtrend/ct5361/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_CT5361
+
+config SYS_BOARD
+	default "ct5361"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_ct5361"
+
+endif
diff --git a/board/comtrend/ct5361/MAINTAINERS b/board/comtrend/ct5361/MAINTAINERS
new file mode 100644
index 0000000..aea737a
--- /dev/null
+++ b/board/comtrend/ct5361/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND CT-5361 BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/ct-5361/
+F:	include/configs/comtrend_ct5361.h
+F:	configs/comtrend_ct5361_ram_defconfig
diff --git a/board/comtrend/ct5361/Makefile b/board/comtrend/ct5361/Makefile
new file mode 100644
index 0000000..872e80a
--- /dev/null
+++ b/board/comtrend/ct5361/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ct-5361.o
diff --git a/board/comtrend/ct5361/ct-5361.c b/board/comtrend/ct5361/ct-5361.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/comtrend/ct5361/ct-5361.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig
new file mode 100644
index 0000000..9ec0c41
--- /dev/null
+++ b/configs/comtrend_ct5361_ram_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BAUDRATE=115200
+CONFIG_BCM6345_CLK=y
+CONFIG_BCM6345_GPIO=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BMIPS_BOOT_RAM=y
+CONFIG_BOARD_COMTREND_CT5361=y
+CONFIG_CFI_FLASH=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_FLASH=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
+CONFIG_SOC_BMIPS_BCM6348=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_PROMPT="CT-5361 # "
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_WDT=y
+CONFIG_WDT_BCM6345=y
diff --git a/include/configs/comtrend_ct5361.h b/include/configs/comtrend_ct5361.h
new file mode 100644
index 0000000..099684d
--- /dev/null
+++ b/include/configs/comtrend_ct5361.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6348.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
-- 
2.1.4

[U-Boot] [PATCH v3 0/6] mips: bmips: add BCM6348 SoC support*

[Daniel Schwierzeck]

Am 16.05.2017 um 18:38 schrieb Álvaro Fernández Rojas:
> BCM6348 is one of the first BCM63xx SoCs and prior to BCM6358, which means
> that it also needs ioremap "hacks".
> Appart from that, rev a1 BCM6348 SoCs have a HW bug and it's pll_conf
> register can't be used to perform reboots.
> 
> v3: introduce changes requested by Simon Glass.
> v2: minor fixes.
> 
> Álvaro Fernández Rojas (6):
>   dm: cpu: bmips: rename cpu_desc specific functions
>   dm: cpu: bmips: add BCM6348 support
>   dm: ram: bmips: split bcm6358_get_ram_size
>   dm: ram: bmips: add BCM6338/BCM6348 support
>   MIPS: add support for Broadcom MIPS BCM6348 SoC family
>   MIPS: add BMIPS Comtrend CT-5361 board
> 
>  arch/mips/dts/Makefile                    |   1 +
>  arch/mips/dts/brcm,bcm6348.dtsi           | 127 ++++++++++++++++++++++++++++++
>  arch/mips/dts/comtrend,ct-5361.dts        |  49 ++++++++++++
>  arch/mips/mach-bmips/Kconfig              |  24 ++++++
>  arch/mips/mach-bmips/include/ioremap.h    |   3 +-
>  board/comtrend/ct5361/Kconfig             |  12 +++
>  board/comtrend/ct5361/MAINTAINERS         |   6 ++
>  board/comtrend/ct5361/Makefile            |   5 ++
>  board/comtrend/ct5361/ct-5361.c           |   7 ++
>  configs/comtrend_ct5361_ram_defconfig     |  57 ++++++++++++++
>  drivers/cpu/bmips_cpu.c                   |  44 +++++++++--
>  drivers/ram/bmips_ram.c                   |  54 ++++++++++---
>  include/configs/bmips_bcm6348.h           |  30 +++++++
>  include/configs/comtrend_ct5361.h         |  20 +++++
>  include/dt-bindings/clock/bcm6348-clock.h |  22 ++++++
>  include/dt-bindings/reset/bcm6348-reset.h |  22 ++++++
>  16 files changed, 467 insertions(+), 16 deletions(-)
>  create mode 100644 arch/mips/dts/brcm,bcm6348.dtsi
>  create mode 100644 arch/mips/dts/comtrend,ct-5361.dts
>  create mode 100644 board/comtrend/ct5361/Kconfig
>  create mode 100644 board/comtrend/ct5361/MAINTAINERS
>  create mode 100644 board/comtrend/ct5361/Makefile
>  create mode 100644 board/comtrend/ct5361/ct-5361.c
>  create mode 100644 configs/comtrend_ct5361_ram_defconfig
>  create mode 100644 include/configs/bmips_bcm6348.h
>  create mode 100644 include/configs/comtrend_ct5361.h
>  create mode 100644 include/dt-bindings/clock/bcm6348-clock.h
>  create mode 100644 include/dt-bindings/reset/bcm6348-reset.h
> 

series applied to u-boot-mips, thanks.

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