From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ziyuan Xu Date: Mon, 15 May 2017 13:56:57 +0800 Subject: [U-Boot] [PATCH 02/33] mmc: add set_timing entry for timing selection In-Reply-To: <1494827848-22619-1-git-send-email-xzy.xu@rock-chips.com> References: <1494827848-22619-1-git-send-email-xzy.xu@rock-chips.com> Message-ID: <1494827848-22619-2-git-send-email-xzy.xu@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Some controller should do some configuration according to the selected timing. Signed-off-by: Ziyuan Xu --- drivers/mmc/mmc.c | 7 +++++++ include/mmc.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f5b2280..1b3652a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -318,6 +318,12 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, return blkcnt; } +static void mmc_set_timing(struct mmc *mmc, uint timing) +{ + mmc->timing = timing; + mmc_set_ios(mmc); +} + static int mmc_go_idle(struct mmc *mmc) { struct mmc_cmd cmd; @@ -1734,6 +1740,7 @@ int mmc_start_init(struct mmc *mmc) mmc->ddr_mode = 0; mmc_set_bus_width(mmc, 1); mmc_set_clock(mmc, 1); + mmc_set_timing(mmc, MMC_TIMING_LEGACY); /* Reset the Card */ err = mmc_go_idle(mmc); diff --git a/include/mmc.h b/include/mmc.h index 0bae1a1..68b6790 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -434,6 +434,21 @@ struct mmc { uint has_init; int high_capacity; uint bus_width; + uint timing; + +#define MMC_TIMING_LEGACY 0 +#define MMC_TIMING_MMC_HS 1 +#define MMC_TIMING_SD_HS 2 +#define MMC_TIMING_UHS_SDR12 3 +#define MMC_TIMING_UHS_SDR25 4 +#define MMC_TIMING_UHS_SDR50 5 +#define MMC_TIMING_UHS_SDR104 6 +#define MMC_TIMING_UHS_DDR50 7 +#define MMC_TIMING_MMC_DDR52 8 +#define MMC_TIMING_MMC_HS200 9 +#define MMC_TIMING_MMC_HS400 10 +#define MMC_TIMING_MMC_HS400ES 11 + uint clock; uint card_caps; uint ocr; @@ -493,6 +508,40 @@ enum mmc_hwpart_conf_mode { MMC_HWPART_CONF_COMPLETE, }; +static inline bool mmc_card_hs(struct mmc *mmc) +{ + return (mmc->timing == MMC_TIMING_MMC_HS) || + (mmc->timing == MMC_TIMING_SD_HS); +} + +static inline bool mmc_card_ddr(struct mmc *mmc) +{ + return (mmc->timing == MMC_TIMING_UHS_DDR50) || + (mmc->timing == MMC_TIMING_MMC_DDR52) || + (mmc->timing == MMC_TIMING_MMC_HS400) || + (mmc->timing == MMC_TIMING_MMC_HS400ES); +} + +static inline bool mmc_card_hs200(struct mmc *mmc) +{ + return mmc->timing == MMC_TIMING_MMC_HS200; +} + +static inline bool mmc_card_ddr52(struct mmc *mmc) +{ + return mmc->timing == MMC_TIMING_MMC_DDR52; +} + +static inline bool mmc_card_hs400(struct mmc *mmc) +{ + return mmc->timing == MMC_TIMING_MMC_HS400; +} + +static inline bool mmc_card_hs400es(struct mmc *mmc) +{ + return mmc->timing == MMC_TIMING_MMC_HS400ES; +} + struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); /** -- 2.7.4