From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Mon, 22 May 2017 20:21:31 +0200 Subject: [U-Boot] [PATCH v2 04/10] mips: bmips: add bcm63xx-spi driver support for BCM6338 In-Reply-To: <1495477297-29230-1-git-send-email-noltari@gmail.com> References: <1495135788-9152-1-git-send-email-noltari@gmail.com> <1495477297-29230-1-git-send-email-noltari@gmail.com> Message-ID: <1495477297-29230-5-git-send-email-noltari@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de This driver manages the SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas --- v2: add spi alias arch/mips/dts/brcm,bcm6338.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index eb51a43..98bda9c 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6338"; + aliases { + spi0 = &spi; + }; + cpus { reg = <0xfffe0000 0x4>; #address-cells = <1>; @@ -109,6 +113,19 @@ status = "disabled"; }; + spi: spi at fffe0c00 { + compatible = "brcm,bcm6338-spi"; + reg = <0xfffe0c00 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6338_CLK_SPI>; + resets = <&periph_rst BCM6338_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + memory-controller at fffe3100 { compatible = "brcm,bcm6338-mc"; reg = <0xfffe3100 0x38>; -- 2.1.4