From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1035728AbdEXUmR (ORCPT ); Wed, 24 May 2017 16:42:17 -0400 Received: from mail-bl2nam02on0085.outbound.protection.outlook.com ([104.47.38.85]:3520 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1032964AbdEXUmL (ORCPT ); Wed, 24 May 2017 16:42:11 -0400 Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=amd.com; From: Yazen Ghannam To: CC: Borislav Petkov , Tony Luck , , , Yazen Ghannam Subject: [PATCH 3/3] x86/mce/AMD: Use saved threshold block info in interrupt handler Date: Wed, 24 May 2017 15:41:47 -0500 Message-ID: <1495658507-7413-3-git-send-email-Yazen.Ghannam@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495658507-7413-1-git-send-email-Yazen.Ghannam@amd.com> References: <1495658507-7413-1-git-send-email-Yazen.Ghannam@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.78.1] X-ClientProxiedBy: DM5PR20CA0046.namprd20.prod.outlook.com (10.171.161.160) To CY4PR1201MB0133.namprd12.prod.outlook.com (10.172.78.15) X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PR1201MB0133: X-MS-Office365-Filtering-Correlation-Id: 29f3b1a3-5f6e-4f13-8987-08d4a2e5590f X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(48565401081)(201703131423075)(201703031133081);SRVR:CY4PR1201MB0133; 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However, we already have the address saved in the threshold blocks list for each CPU and bank. The list only contains blocks that have passed all the valid checks. Besides the redundancy, there's also an smp_call_function* in get_block_address() and this causes a warning when servicing the interrupt. WARNING: CPU: 0 PID: 0 at kernel/smp.c:281 smp_call_function_single+0xdd/0xf0 ... Call Trace: rdmsr_safe_on_cpu+0x5d/0x90 get_block_address.isra.2+0x97/0x100 amd_threshold_interrupt+0xae/0x220 smp_threshold_interrupt+0x1b/0x40 threshold_interrupt+0x89/0x90 Iterate over the threshold blocks list and use the saved address. Also, drop the redundant valid checks. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 2074b870..14e4dab 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -873,30 +873,23 @@ static void log_error_thresholding(unsigned int bank, u64 misc) */ static void amd_threshold_interrupt(void) { - u32 low = 0, high = 0, address = 0; - unsigned int bank, block, cpu = smp_processor_id(); + u32 low = 0, high = 0; + unsigned int bank, cpu = smp_processor_id(); struct thresh_restart tr; + struct threshold_block *block = NULL, *tmp = NULL; + struct list_head *head = NULL; for (bank = 0; bank < mca_cfg.banks; ++bank) { if (!(per_cpu(bank_map, cpu) & (1 << bank))) continue; - for (block = 0; block < NR_BLOCKS; ++block) { - address = get_block_address(cpu, address, low, high, bank, block); - if (!address) - break; - if (rdmsr_safe(address, &low, &high)) - break; + if (!per_cpu(threshold_banks, cpu)[bank]->blocks) + continue; - if (!(high & MASK_VALID_HI)) { - if (block) - continue; - else - break; - } + head = &per_cpu(threshold_banks, cpu)[bank]->blocks_head; - if (!(high & MASK_CNTP_HI) || - (high & MASK_LOCKED_HI)) + list_for_each_entry_safe(block, tmp, head, miscj) { + if (rdmsr_safe(block->address, &low, &high)) continue; if (!(high & MASK_OVERFLOW_HI)) @@ -907,7 +900,7 @@ static void amd_threshold_interrupt(void) /* Reset threshold block after logging error. */ memset(&tr, 0, sizeof(tr)); - tr.b = &per_cpu(threshold_banks, cpu)[bank]->blocks[block]; + tr.b = block; threshold_restart_bank(&tr); } } -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [3/3] x86/mce/AMD: Use saved threshold block info in interrupt handler From: Yazen Ghannam Message-Id: <1495658507-7413-3-git-send-email-Yazen.Ghannam@amd.com> Date: Wed, 24 May 2017 15:41:47 -0500 To: linux-edac@vger.kernel.org Cc: Borislav Petkov , Tony Luck , x86@kernel.org, linux-kernel@vger.kernel.org, Yazen Ghannam List-ID: RnJvbTogWWF6ZW4gR2hhbm5hbSA8eWF6ZW4uZ2hhbm5hbUBhbWQuY29tPgoKSW4gdGhlIGFtZF90 aHJlc2hvbGRfaW50ZXJydXB0KCkgaGFuZGxlciwgd2UgbG9vcCB0aHJvdWdoIGV2ZXJ5IHBvc3Np YmxlCmJsb2NrIGluIGVhY2ggYmFuayBhbmQgcmVkaXNjb3ZlciB0aGUgYmxvY2sncyBhZGRyZXNz IGFuZCBpZiBpdCdzIHZhbGlkLAplLmcuIHZhbGlkLCBjb3VudGVyIHByZXNlbnQgYW5kIG5vdCBs b2NrZWQuIEhvd2V2ZXIsIHdlIGFscmVhZHkgaGF2ZSB0aGUKYWRkcmVzcyBzYXZlZCBpbiB0aGUg dGhyZXNob2xkIGJsb2NrcyBsaXN0IGZvciBlYWNoIENQVSBhbmQgYmFuay4gVGhlIGxpc3QKb25s eSBjb250YWlucyBibG9ja3MgdGhhdCBoYXZlIHBhc3NlZCBhbGwgdGhlIHZhbGlkIGNoZWNrcy4K CkJlc2lkZXMgdGhlIHJlZHVuZGFuY3ksIHRoZXJlJ3MgYWxzbyBhbiBzbXBfY2FsbF9mdW5jdGlv biogaW4KZ2V0X2Jsb2NrX2FkZHJlc3MoKSBhbmQgdGhpcyBjYXVzZXMgYSB3YXJuaW5nIHdoZW4g c2VydmljaW5nIHRoZSBpbnRlcnJ1cHQuCgogV0FSTklORzogQ1BVOiAwIFBJRDogMCBhdCBrZXJu ZWwvc21wLmM6MjgxIHNtcF9jYWxsX2Z1bmN0aW9uX3NpbmdsZSsweGRkLzB4ZjAKIC4uLgogQ2Fs bCBUcmFjZToKICA8SVJRPgogIHJkbXNyX3NhZmVfb25fY3B1KzB4NWQvMHg5MAogIGdldF9ibG9j a19hZGRyZXNzLmlzcmEuMisweDk3LzB4MTAwCiAgYW1kX3RocmVzaG9sZF9pbnRlcnJ1cHQrMHhh ZS8weDIyMAogIHNtcF90aHJlc2hvbGRfaW50ZXJydXB0KzB4MWIvMHg0MAogIHRocmVzaG9sZF9p bnRlcnJ1cHQrMHg4OS8weDkwCgpJdGVyYXRlIG92ZXIgdGhlIHRocmVzaG9sZCBibG9ja3MgbGlz dCBhbmQgdXNlIHRoZSBzYXZlZCBhZGRyZXNzLiBBbHNvLApkcm9wIHRoZSByZWR1bmRhbnQgdmFs aWQgY2hlY2tzLgoKU2lnbmVkLW9mZi1ieTogWWF6ZW4gR2hhbm5hbSA8eWF6ZW4uZ2hhbm5hbUBh bWQuY29tPgotLS0KIGFyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZV9hbWQuYyB8IDI3ICsr KysrKysrKystLS0tLS0tLS0tLS0tLS0tLQogMSBmaWxlIGNoYW5nZWQsIDEwIGluc2VydGlvbnMo KyksIDE3IGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNo ZWNrL21jZV9hbWQuYyBiL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZV9hbWQuYwppbmRl eCAyMDc0Yjg3MC4uMTRlNGRhYiAxMDA2NDQKLS0tIGEvYXJjaC94ODYva2VybmVsL2NwdS9tY2hl Y2svbWNlX2FtZC5jCisrKyBiL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZV9hbWQuYwpA QCAtODczLDMwICs4NzMsMjMgQEAgc3RhdGljIHZvaWQgbG9nX2Vycm9yX3RocmVzaG9sZGluZyh1 bnNpZ25lZCBpbnQgYmFuaywgdTY0IG1pc2MpCiAgKi8KIHN0YXRpYyB2b2lkIGFtZF90aHJlc2hv bGRfaW50ZXJydXB0KHZvaWQpCiB7Ci0JdTMyIGxvdyA9IDAsIGhpZ2ggPSAwLCBhZGRyZXNzID0g MDsKLQl1bnNpZ25lZCBpbnQgYmFuaywgYmxvY2ssIGNwdSA9IHNtcF9wcm9jZXNzb3JfaWQoKTsK Kwl1MzIgbG93ID0gMCwgaGlnaCA9IDA7CisJdW5zaWduZWQgaW50IGJhbmssIGNwdSA9IHNtcF9w cm9jZXNzb3JfaWQoKTsKIAlzdHJ1Y3QgdGhyZXNoX3Jlc3RhcnQgdHI7CisJc3RydWN0IHRocmVz aG9sZF9ibG9jayAqYmxvY2sgPSBOVUxMLCAqdG1wID0gTlVMTDsKKwlzdHJ1Y3QgbGlzdF9oZWFk ICpoZWFkID0gTlVMTDsKIAogCWZvciAoYmFuayA9IDA7IGJhbmsgPCBtY2FfY2ZnLmJhbmtzOyAr K2JhbmspIHsKIAkJaWYgKCEocGVyX2NwdShiYW5rX21hcCwgY3B1KSAmICgxIDw8IGJhbmspKSkK IAkJCWNvbnRpbnVlOwotCQlmb3IgKGJsb2NrID0gMDsgYmxvY2sgPCBOUl9CTE9DS1M7ICsrYmxv Y2spIHsKLQkJCWFkZHJlc3MgPSBnZXRfYmxvY2tfYWRkcmVzcyhjcHUsIGFkZHJlc3MsIGxvdywg aGlnaCwgYmFuaywgYmxvY2spOwotCQkJaWYgKCFhZGRyZXNzKQotCQkJCWJyZWFrOwogCi0JCQlp ZiAocmRtc3Jfc2FmZShhZGRyZXNzLCAmbG93LCAmaGlnaCkpCi0JCQkJYnJlYWs7CisJCWlmICgh cGVyX2NwdSh0aHJlc2hvbGRfYmFua3MsIGNwdSlbYmFua10tPmJsb2NrcykKKwkJCWNvbnRpbnVl OwogCi0JCQlpZiAoIShoaWdoICYgTUFTS19WQUxJRF9ISSkpIHsKLQkJCQlpZiAoYmxvY2spCi0J CQkJCWNvbnRpbnVlOwotCQkJCWVsc2UKLQkJCQkJYnJlYWs7Ci0JCQl9CisJCWhlYWQgPSAmcGVy X2NwdSh0aHJlc2hvbGRfYmFua3MsIGNwdSlbYmFua10tPmJsb2Nrc19oZWFkOwogCi0JCQlpZiAo IShoaWdoICYgTUFTS19DTlRQX0hJKSAgfHwKLQkJCSAgICAgKGhpZ2ggJiBNQVNLX0xPQ0tFRF9I SSkpCisJCWxpc3RfZm9yX2VhY2hfZW50cnlfc2FmZShibG9jaywgdG1wLCBoZWFkLCBtaXNjaikg eworCQkJaWYgKHJkbXNyX3NhZmUoYmxvY2stPmFkZHJlc3MsICZsb3csICZoaWdoKSkKIAkJCQlj b250aW51ZTsKIAogCQkJaWYgKCEoaGlnaCAmIE1BU0tfT1ZFUkZMT1dfSEkpKQpAQCAtOTA3LDcg KzkwMCw3IEBAIHN0YXRpYyB2b2lkIGFtZF90aHJlc2hvbGRfaW50ZXJydXB0KHZvaWQpCiAKIAkJ CS8qIFJlc2V0IHRocmVzaG9sZCBibG9jayBhZnRlciBsb2dnaW5nIGVycm9yLiAqLwogCQkJbWVt c2V0KCZ0ciwgMCwgc2l6ZW9mKHRyKSk7Ci0JCQl0ci5iID0gJnBlcl9jcHUodGhyZXNob2xkX2Jh bmtzLCBjcHUpW2JhbmtdLT5ibG9ja3NbYmxvY2tdOworCQkJdHIuYiA9IGJsb2NrOwogCQkJdGhy ZXNob2xkX3Jlc3RhcnRfYmFuaygmdHIpOwogCQl9CiAJfQo=