From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751416AbdFBGg6 (ORCPT ); Fri, 2 Jun 2017 02:36:58 -0400 Received: from mail-wm0-f43.google.com ([74.125.82.43]:36487 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751141AbdFBGg4 (ORCPT ); Fri, 2 Jun 2017 02:36:56 -0400 From: Anup Patel To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: Catalin Marinas , Will Deacon , Ray Jui , Scott Branden , Jon Mason , Florian Fainelli , Oza Pawandeep , Srinath Mannam , Pramod Kumar , Sandeep Tripathy , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, Anup Patel Subject: [PATCH v6 10/11] arm64: dts: Add PL022, PL330 and SP805 DT nodes for Stingray Date: Fri, 2 Jun 2017 12:04:34 +0530 Message-Id: <1496385275-6899-11-git-send-email-anup.patel@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496385275-6899-1-git-send-email-anup.patel@broadcom.com> References: <1496385275-6899-1-git-send-email-anup.patel@broadcom.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We have two instance of PL022 SPI controllers, one instance of DMA PL330, and one non-secure SP805 Watchdog on Stingray SOC. This patch adds DT nodes for the above mentioned devices in Stingray DT. Signed-off-by: Anup Patel Reviewed-by: Pramod KUMAR Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- .../boot/dts/broadcom/stingray/bcm958742k.dts | 30 +++++++++++++ .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 52 ++++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts index c309cda..5671669 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts @@ -46,3 +46,33 @@ &uart3 { status = "okay"; }; + +&ssp0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio_hsls 34 0>; + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&ssp1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio_hsls 96 0>; + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 91ba61e..88a6176 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -279,6 +279,14 @@ status = "disabled"; }; + wdt0: watchdog@000c0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x000c0000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; + clock-names = "wdogclk", "apb_pclk"; + }; + gpio_hsls: gpio@000d0000 { compatible = "brcm,iproc-gpio"; reg = <0x000d0000 0x864>; @@ -359,11 +367,55 @@ status = "disabled"; }; + ssp0: ssp@00180000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00180000 0x1000>; + interrupts = ; + clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; + clock-names = "spiclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp1: ssp@00190000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00190000 0x1000>; + interrupts = ; + clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; + clock-names = "spiclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + hwrng: hwrng@00220000 { compatible = "brcm,iproc-rng200"; reg = <0x00220000 0x28>; }; + dma0: dma@00310000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x00310000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&hsls_div2_clk>; + clock-names = "apb_pclk"; + iommus = <&smmu 0x6000 0x0000>; + }; + nand: nand@00360000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x00360000 0x600>, -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: anup.patel@broadcom.com (Anup Patel) Date: Fri, 2 Jun 2017 12:04:34 +0530 Subject: [PATCH v6 10/11] arm64: dts: Add PL022, PL330 and SP805 DT nodes for Stingray In-Reply-To: <1496385275-6899-1-git-send-email-anup.patel@broadcom.com> References: <1496385275-6899-1-git-send-email-anup.patel@broadcom.com> Message-ID: <1496385275-6899-11-git-send-email-anup.patel@broadcom.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org We have two instance of PL022 SPI controllers, one instance of DMA PL330, and one non-secure SP805 Watchdog on Stingray SOC. This patch adds DT nodes for the above mentioned devices in Stingray DT. Signed-off-by: Anup Patel Reviewed-by: Pramod KUMAR Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- .../boot/dts/broadcom/stingray/bcm958742k.dts | 30 +++++++++++++ .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 52 ++++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts index c309cda..5671669 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts @@ -46,3 +46,33 @@ &uart3 { status = "okay"; }; + +&ssp0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio_hsls 34 0>; + status = "okay"; + + spi-flash at 0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&ssp1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio_hsls 96 0>; + status = "okay"; + + spi-flash at 0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 91ba61e..88a6176 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -279,6 +279,14 @@ status = "disabled"; }; + wdt0: watchdog at 000c0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x000c0000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; + clock-names = "wdogclk", "apb_pclk"; + }; + gpio_hsls: gpio at 000d0000 { compatible = "brcm,iproc-gpio"; reg = <0x000d0000 0x864>; @@ -359,11 +367,55 @@ status = "disabled"; }; + ssp0: ssp at 00180000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00180000 0x1000>; + interrupts = ; + clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; + clock-names = "spiclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp1: ssp at 00190000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00190000 0x1000>; + interrupts = ; + clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; + clock-names = "spiclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + hwrng: hwrng at 00220000 { compatible = "brcm,iproc-rng200"; reg = <0x00220000 0x28>; }; + dma0: dma at 00310000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x00310000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&hsls_div2_clk>; + clock-names = "apb_pclk"; + iommus = <&smmu 0x6000 0x0000>; + }; + nand: nand at 00360000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x00360000 0x600>, -- 2.7.4