diff for duplicates of <1496385275-6899-5-git-send-email-anup.patel@broadcom.com>
diff --git a/a/1.txt b/N1/1.txt
index 2967e5c..42e256d 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -261,7 +261,7 @@ index 0000000..61133b7
+ #address-cells = <2>;
+ #size-cells = <0>;
+
-+ cpu@000 {
++ cpu at 000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x0>;
@@ -269,7 +269,7 @@ index 0000000..61133b7
+ next-level-cache = <&CLUSTER0_L2>;
+ };
+
-+ cpu@001 {
++ cpu at 001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x1>;
@@ -277,7 +277,7 @@ index 0000000..61133b7
+ next-level-cache = <&CLUSTER0_L2>;
+ };
+
-+ cpu@100 {
++ cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x100>;
@@ -285,7 +285,7 @@ index 0000000..61133b7
+ next-level-cache = <&CLUSTER1_L2>;
+ };
+
-+ cpu@101 {
++ cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x101>;
@@ -293,7 +293,7 @@ index 0000000..61133b7
+ next-level-cache = <&CLUSTER1_L2>;
+ };
+
-+ cpu@200 {
++ cpu at 200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x200>;
@@ -301,7 +301,7 @@ index 0000000..61133b7
+ next-level-cache = <&CLUSTER2_L2>;
+ };
+
-+ cpu@201 {
++ cpu at 201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x201>;
@@ -309,7 +309,7 @@ index 0000000..61133b7
+ next-level-cache = <&CLUSTER2_L2>;
+ };
+
-+ cpu@300 {
++ cpu at 300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x300>;
@@ -317,7 +317,7 @@ index 0000000..61133b7
+ next-level-cache = <&CLUSTER3_L2>;
+ };
+
-+ cpu@301 {
++ cpu at 301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x301>;
@@ -325,24 +325,24 @@ index 0000000..61133b7
+ next-level-cache = <&CLUSTER3_L2>;
+ };
+
-+ CLUSTER0_L2: l2-cache@000 {
++ CLUSTER0_L2: l2-cache at 000 {
+ compatible = "cache";
+ };
+
-+ CLUSTER1_L2: l2-cache@100 {
++ CLUSTER1_L2: l2-cache at 100 {
+ compatible = "cache";
+ };
+
-+ CLUSTER2_L2: l2-cache@200 {
++ CLUSTER2_L2: l2-cache at 200 {
+ compatible = "cache";
+ };
+
-+ CLUSTER3_L2: l2-cache@300 {
++ CLUSTER3_L2: l2-cache at 300 {
+ compatible = "cache";
+ };
+ };
+
-+ memory: memory@80000000 {
++ memory: memory at 80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ };
@@ -371,7 +371,7 @@ index 0000000..61133b7
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x61000000 0x05000000>;
+
-+ gic: interrupt-controller@02c00000 {
++ gic: interrupt-controller at 02c00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
@@ -382,7 +382,7 @@ index 0000000..61133b7
+ <0x02e00000 0x600000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
-+ gic_its: gic-its@63c20000 {
++ gic_its: gic-its at 63c20000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
@@ -390,7 +390,7 @@ index 0000000..61133b7
+ };
+ };
+
-+ smmu: mmu@03000000 {
++ smmu: mmu at 03000000 {
+ compatible = "arm,mmu-500";
+ reg = <0x03000000 0x80000>;
+ #global-interrupts = <1>;
@@ -469,7 +469,7 @@ index 0000000..61133b7
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x68900000 0x17700000>;
+
-+ uart0: uart@00100000 {
++ uart0: uart at 00100000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00100000 0x1000>;
@@ -480,7 +480,7 @@ index 0000000..61133b7
+ status = "disabled";
+ };
+
-+ uart1: uart@00110000 {
++ uart1: uart at 00110000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00110000 0x1000>;
@@ -491,7 +491,7 @@ index 0000000..61133b7
+ status = "disabled";
+ };
+
-+ uart2: uart@00120000 {
++ uart2: uart at 00120000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00120000 0x1000>;
@@ -502,7 +502,7 @@ index 0000000..61133b7
+ status = "disabled";
+ };
+
-+ uart3: uart@00130000 {
++ uart3: uart at 00130000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00130000 0x1000>;
@@ -513,7 +513,7 @@ index 0000000..61133b7
+ status = "disabled";
+ };
+
-+ hwrng: hwrng@00220000 {
++ hwrng: hwrng at 00220000 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0x00220000 0x28>;
+ };
diff --git a/a/content_digest b/N1/content_digest
index da96244..a3a9dcd 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,7 @@
"ref\0001496385275-6899-1-git-send-email-anup.patel\@broadcom.com\0"
]
[
- "From\0Anup Patel <anup.patel\@broadcom.com>\0"
+ "From\0anup.patel\@broadcom.com (Anup Patel)\0"
]
[
"Subject\0[PATCH v6 04/11] arm64: dts: Initial DTS files for Broadcom Stingray SOC\0"
@@ -11,29 +11,7 @@
"Date\0Fri, 2 Jun 2017 12:04:28 +0530\0"
]
[
- "To\0Rob Herring <robh+dt\@kernel.org>",
- " Mark Rutland <mark.rutland\@arm.com>",
- " Michael Turquette <mturquette\@baylibre.com>",
- " Stephen Boyd <sboyd\@codeaurora.org>\0"
-]
-[
- "Cc\0Catalin Marinas <catalin.marinas\@arm.com>",
- " Will Deacon <will.deacon\@arm.com>",
- " Ray Jui <rjui\@broadcom.com>",
- " Scott Branden <sbranden\@broadcom.com>",
- " Jon Mason <jonmason\@broadcom.com>",
- " Florian Fainelli <f.fainelli\@gmail.com>",
- " Oza Pawandeep <oza.oza\@broadcom.com>",
- " Srinath Mannam <srinath.mannam\@broadcom.com>",
- " Pramod Kumar <pramod.kumar\@broadcom.com>",
- " Sandeep Tripathy <sandeep.tripathy\@broadcom.com>",
- " devicetree\@vger.kernel.org",
- " linux-kernel\@vger.kernel.org",
- " linux-clk\@vger.kernel.org",
- " linux-arm-kernel\@lists.infradead.org",
- " bcm-kernel-feedback-list\@broadcom.com",
- " Anup Patel <anup.patel\@broadcom.com>",
- " Scott Branden <scott.branden\@broadcom.com>\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -305,7 +283,7 @@
"+\t\t#address-cells = <2>;\n",
"+\t\t#size-cells = <0>;\n",
"+\n",
- "+\t\tcpu\@000 {\n",
+ "+\t\tcpu at 000 {\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n",
"+\t\t\treg = <0x0 0x0>;\n",
@@ -313,7 +291,7 @@
"+\t\t\tnext-level-cache = <&CLUSTER0_L2>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu\@001 {\n",
+ "+\t\tcpu at 001 {\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n",
"+\t\t\treg = <0x0 0x1>;\n",
@@ -321,7 +299,7 @@
"+\t\t\tnext-level-cache = <&CLUSTER0_L2>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu\@100 {\n",
+ "+\t\tcpu at 100 {\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n",
"+\t\t\treg = <0x0 0x100>;\n",
@@ -329,7 +307,7 @@
"+\t\t\tnext-level-cache = <&CLUSTER1_L2>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu\@101 {\n",
+ "+\t\tcpu at 101 {\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n",
"+\t\t\treg = <0x0 0x101>;\n",
@@ -337,7 +315,7 @@
"+\t\t\tnext-level-cache = <&CLUSTER1_L2>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu\@200 {\n",
+ "+\t\tcpu at 200 {\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n",
"+\t\t\treg = <0x0 0x200>;\n",
@@ -345,7 +323,7 @@
"+\t\t\tnext-level-cache = <&CLUSTER2_L2>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu\@201 {\n",
+ "+\t\tcpu at 201 {\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n",
"+\t\t\treg = <0x0 0x201>;\n",
@@ -353,7 +331,7 @@
"+\t\t\tnext-level-cache = <&CLUSTER2_L2>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu\@300 {\n",
+ "+\t\tcpu at 300 {\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n",
"+\t\t\treg = <0x0 0x300>;\n",
@@ -361,7 +339,7 @@
"+\t\t\tnext-level-cache = <&CLUSTER3_L2>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu\@301 {\n",
+ "+\t\tcpu at 301 {\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n",
"+\t\t\treg = <0x0 0x301>;\n",
@@ -369,24 +347,24 @@
"+\t\t\tnext-level-cache = <&CLUSTER3_L2>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tCLUSTER0_L2: l2-cache\@000 {\n",
+ "+\t\tCLUSTER0_L2: l2-cache at 000 {\n",
"+\t\t\tcompatible = \"cache\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tCLUSTER1_L2: l2-cache\@100 {\n",
+ "+\t\tCLUSTER1_L2: l2-cache at 100 {\n",
"+\t\t\tcompatible = \"cache\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tCLUSTER2_L2: l2-cache\@200 {\n",
+ "+\t\tCLUSTER2_L2: l2-cache at 200 {\n",
"+\t\t\tcompatible = \"cache\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tCLUSTER3_L2: l2-cache\@300 {\n",
+ "+\t\tCLUSTER3_L2: l2-cache at 300 {\n",
"+\t\t\tcompatible = \"cache\";\n",
"+\t\t};\n",
"+\t};\n",
"+\n",
- "+\tmemory: memory\@80000000 {\n",
+ "+\tmemory: memory at 80000000 {\n",
"+\t\tdevice_type = \"memory\";\n",
"+\t\treg = <0x00000000 0x80000000 0 0x40000000>;\n",
"+\t};\n",
@@ -415,7 +393,7 @@
"+\t\t#size-cells = <1>;\n",
"+\t\tranges = <0x0 0x0 0x61000000 0x05000000>;\n",
"+\n",
- "+\t\tgic: interrupt-controller\@02c00000 {\n",
+ "+\t\tgic: interrupt-controller at 02c00000 {\n",
"+\t\t\tcompatible = \"arm,gic-v3\";\n",
"+\t\t\t#interrupt-cells = <3>;\n",
"+\t\t\t#address-cells = <1>;\n",
@@ -426,7 +404,7 @@
"+\t\t\t <0x02e00000 0x600000>; /* GICR */\n",
"+\t\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n",
"+\n",
- "+\t\t\tgic_its: gic-its\@63c20000 {\n",
+ "+\t\t\tgic_its: gic-its at 63c20000 {\n",
"+\t\t\t\tcompatible = \"arm,gic-v3-its\";\n",
"+\t\t\t\tmsi-controller;\n",
"+\t\t\t\t#msi-cells = <1>;\n",
@@ -434,7 +412,7 @@
"+\t\t\t};\n",
"+\t\t};\n",
"+\n",
- "+\t\tsmmu: mmu\@03000000 {\n",
+ "+\t\tsmmu: mmu at 03000000 {\n",
"+\t\t\tcompatible = \"arm,mmu-500\";\n",
"+\t\t\treg = <0x03000000 0x80000>;\n",
"+\t\t\t#global-interrupts = <1>;\n",
@@ -513,7 +491,7 @@
"+\t\t#size-cells = <1>;\n",
"+\t\tranges = <0x0 0x0 0x68900000 0x17700000>;\n",
"+\n",
- "+\t\tuart0: uart\@00100000 {\n",
+ "+\t\tuart0: uart at 00100000 {\n",
"+\t\t\tdevice_type = \"serial\";\n",
"+\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"+\t\t\treg = <0x00100000 0x1000>;\n",
@@ -524,7 +502,7 @@
"+\t\t\tstatus = \"disabled\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tuart1: uart\@00110000 {\n",
+ "+\t\tuart1: uart at 00110000 {\n",
"+\t\t\tdevice_type = \"serial\";\n",
"+\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"+\t\t\treg = <0x00110000 0x1000>;\n",
@@ -535,7 +513,7 @@
"+\t\t\tstatus = \"disabled\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tuart2: uart\@00120000 {\n",
+ "+\t\tuart2: uart at 00120000 {\n",
"+\t\t\tdevice_type = \"serial\";\n",
"+\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"+\t\t\treg = <0x00120000 0x1000>;\n",
@@ -546,7 +524,7 @@
"+\t\t\tstatus = \"disabled\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tuart3: uart\@00130000 {\n",
+ "+\t\tuart3: uart at 00130000 {\n",
"+\t\t\tdevice_type = \"serial\";\n",
"+\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"+\t\t\treg = <0x00130000 0x1000>;\n",
@@ -557,7 +535,7 @@
"+\t\t\tstatus = \"disabled\";\n",
"+\t\t};\n",
"+\n",
- "+\t\thwrng: hwrng\@00220000 {\n",
+ "+\t\thwrng: hwrng at 00220000 {\n",
"+\t\t\tcompatible = \"brcm,iproc-rng200\";\n",
"+\t\t\treg = <0x00220000 0x28>;\n",
"+\t\t};\n",
@@ -567,4 +545,4 @@
"2.7.4"
]
-0be1e0c102ae76e81c171a3d439df954c90a39021c1f2b749eda2aa8202523f9
+4ea38819498157002feeba3bdbdbff44cea197721fe89b9f9634d723a3f934b1
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