From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chee, Tien Fong Date: Tue, 6 Jun 2017 09:36:06 +0000 Subject: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL In-Reply-To: <38c8b2ad-935c-0e82-b7c6-4f1b793e023d@denx.de> References: <1496730959-13353-1-git-send-email-tien.fong.chee@intel.com> <1496730959-13353-5-git-send-email-tien.fong.chee@intel.com> <1496737192.2428.52.camel@intel.com> <38c8b2ad-935c-0e82-b7c6-4f1b793e023d@denx.de> Message-ID: <1496741766.2428.60.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote: > On 06/06/2017 10:19 AM, Chee, Tien Fong wrote: > > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote: > > > > > > On 06/06/2017 08:35 AM, tien.fong.chee at intel.com wrote: > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > This patch is for enabling FPGA driver support on SPL > > > Why would we want that on Gen5 ? I believe this is only needed on > > > Gen10. > > > > > I already moved the fpga_manager driver into drivers/fpga/ on patch > > 6, > > and fpga_manager drivers are required on SPL. Actually fpga_manager > > driver should be part of the drivers/fpga. > I think I miss some fundamental piece of information . Why would I > need > anything from the FPGA framework in SPL on Gen5 ? It is not needed > thus > far. Is it because you shuffled some of the code around or what ? > Because we need to know some status and mode type from FPGA even we did not program FPGA in SPL. > > > > > > > > > > > > > > > > > Signed-off-by: Tien Fong Chee > > > > --- > > > >  configs/socfpga_arria5_defconfig       | 1 + > > > >  configs/socfpga_cyclone5_defconfig     | 1 + > > > >  configs/socfpga_de0_nano_soc_defconfig | 1 + > > > >  configs/socfpga_de10_nano_defconfig    | 1 + > > > >  configs/socfpga_de1_soc_defconfig      | 1 + > > > >  configs/socfpga_is1_defconfig          | 1 + > > > >  configs/socfpga_mcvevk_defconfig       | 1 + > > > >  configs/socfpga_sockit_defconfig       | 1 + > > > >  configs/socfpga_socrates_defconfig     | 1 + > > > >  configs/socfpga_sr1500_defconfig       | 1 + > > > >  configs/socfpga_vining_fpga_defconfig  | 1 + > > > >  11 files changed, 11 insertions(+) > > > > > > > > diff --git a/configs/socfpga_arria5_defconfig > > > > b/configs/socfpga_arria5_defconfig > > > > index 6f2a06f..4b1e252 100644 > > > > --- a/configs/socfpga_arria5_defconfig > > > > +++ b/configs/socfpga_arria5_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > >  CONFIG_SPL=y > > > >  CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > >  # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_cyclone5_defconfig > > > > b/configs/socfpga_cyclone5_defconfig > > > > index 1047657..fe7ac08 100644 > > > > --- a/configs/socfpga_cyclone5_defconfig > > > > +++ b/configs/socfpga_cyclone5_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > >  CONFIG_SPL=y > > > >  CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > >  # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_de0_nano_soc_defconfig > > > > b/configs/socfpga_de0_nano_soc_defconfig > > > > index 72a9e5d..d86a9d6 100644 > > > > --- a/configs/socfpga_de0_nano_soc_defconfig > > > > +++ b/configs/socfpga_de0_nano_soc_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > >  CONFIG_SPL=y > > > >  CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > >  # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_de10_nano_defconfig > > > > b/configs/socfpga_de10_nano_defconfig > > > > index 67864cf..ac8ca70 100644 > > > > --- a/configs/socfpga_de10_nano_defconfig > > > > +++ b/configs/socfpga_de10_nano_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > >  CONFIG_SPL=y > > > >  CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > >  # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_de1_soc_defconfig > > > > b/configs/socfpga_de1_soc_defconfig > > > > index 35c4484..cc0a35d 100644 > > > > --- a/configs/socfpga_de1_soc_defconfig > > > > +++ b/configs/socfpga_de1_soc_defconfig > > > > @@ -16,6 +16,7 @@ CONFIG_SPL=y > > > >  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > > > >  CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_SPL_YMODEM_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > > diff --git a/configs/socfpga_is1_defconfig > > > > b/configs/socfpga_is1_defconfig > > > > index ae688f8..ccfed7a 100644 > > > > --- a/configs/socfpga_is1_defconfig > > > > +++ b/configs/socfpga_is1_defconfig > > > > @@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y > > > >  # CONFIG_DISPLAY_BOARDINFO is not set > > > >  CONFIG_SPL=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > >  # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_mcvevk_defconfig > > > > b/configs/socfpga_mcvevk_defconfig > > > > index c5e3b7b..9bcb47d 100644 > > > > --- a/configs/socfpga_mcvevk_defconfig > > > > +++ b/configs/socfpga_mcvevk_defconfig > > > > @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y > > > >  CONFIG_SPL=y > > > >  CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > >  # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_sockit_defconfig > > > > b/configs/socfpga_sockit_defconfig > > > > index 3ff7bb7..ef54e1f 100644 > > > > --- a/configs/socfpga_sockit_defconfig > > > > +++ b/configs/socfpga_sockit_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > >  CONFIG_SPL=y > > > >  CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > >  # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_socrates_defconfig > > > > b/configs/socfpga_socrates_defconfig > > > > index fb9c13f..78daf26 100644 > > > > --- a/configs/socfpga_socrates_defconfig > > > > +++ b/configs/socfpga_socrates_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > >  CONFIG_SPL=y > > > >  CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > >  # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_sr1500_defconfig > > > > b/configs/socfpga_sr1500_defconfig > > > > index d90d6a1..4a12379 100644 > > > > --- a/configs/socfpga_sr1500_defconfig > > > > +++ b/configs/socfpga_sr1500_defconfig > > > > @@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_F=y > > > >  CONFIG_SPL=y > > > >  CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > >  # CONFIG_CMD_IMLS is not set > > > > diff --git a/configs/socfpga_vining_fpga_defconfig > > > > b/configs/socfpga_vining_fpga_defconfig > > > > index c3fbe40..3fc37dc 100644 > > > > --- a/configs/socfpga_vining_fpga_defconfig > > > > +++ b/configs/socfpga_vining_fpga_defconfig > > > > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y > > > >  CONFIG_SPL=y > > > >  CONFIG_SPL_SYS_MALLOC_SIMPLE=y > > > >  CONFIG_SPL_STACK_R=y > > > > +CONFIG_SPL_FPGA_SUPPORT=y > > > >  CONFIG_HUSH_PARSER=y > > > >  CONFIG_CMD_BOOTZ=y > > > >  # CONFIG_CMD_IMLS is not set > > > > >