[PATCH 0/5] enable usb2 function on poplar board.

[PATCH 0/5] enable usb2 function on poplar board.

[Jiancheng Xue]

This patchset is mainly used to enable usb2 function on poplar board.

Jiancheng Xue (4):
  clk: hisilicon: add usb2 clocks for hi3798cv200 SoC
  dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy
  arm64: dts: hisilicon: add usb2 controller and phy nodes for poplar
    board.
  arm64: defconfig: enable some drivers and configs for
    hi3798cv200-poplar board.

Pengcheng Li (1):
  phy: add inno-usb2-phy driver for hi3798cv200 SoC

 .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt |  36 +++
 .../boot/dts/hisilicon/hi3798cv200-poplar.dts      |  13 +
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi     |  47 ++++
 arch/arm64/configs/defconfig                       |  13 +-
 drivers/clk/hisilicon/crg-hi3798cv200.c            |  21 ++
 drivers/phy/Kconfig                                |  10 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-hisi-inno-usb2.c                   | 287 +++++++++++++++++++++
 include/dt-bindings/clock/histb-clock.h            |   9 +-
 9 files changed, 435 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
 create mode 100644 drivers/phy/phy-hisi-inno-usb2.c

-- 
1.9.1

[PATCH 0/5] enable usb2 function on poplar board.

[Jiancheng Xue]

This patchset is mainly used to enable usb2 function on poplar board.

Jiancheng Xue (4):
  clk: hisilicon: add usb2 clocks for hi3798cv200 SoC
  dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy
  arm64: dts: hisilicon: add usb2 controller and phy nodes for poplar
    board.
  arm64: defconfig: enable some drivers and configs for
    hi3798cv200-poplar board.

Pengcheng Li (1):
  phy: add inno-usb2-phy driver for hi3798cv200 SoC

 .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt |  36 +++
 .../boot/dts/hisilicon/hi3798cv200-poplar.dts      |  13 +
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi     |  47 ++++
 arch/arm64/configs/defconfig                       |  13 +-
 drivers/clk/hisilicon/crg-hi3798cv200.c            |  21 ++
 drivers/phy/Kconfig                                |  10 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-hisi-inno-usb2.c                   | 287 +++++++++++++++++++++
 include/dt-bindings/clock/histb-clock.h            |   9 +-
 9 files changed, 435 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
 create mode 100644 drivers/phy/phy-hisi-inno-usb2.c

-- 
1.9.1

[PATCH 0/5] enable usb2 function on poplar board.

[Jiancheng Xue]

This patchset is mainly used to enable usb2 function on poplar board.

Jiancheng Xue (4):
  clk: hisilicon: add usb2 clocks for hi3798cv200 SoC
  dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy
  arm64: dts: hisilicon: add usb2 controller and phy nodes for poplar
    board.
  arm64: defconfig: enable some drivers and configs for
    hi3798cv200-poplar board.

Pengcheng Li (1):
  phy: add inno-usb2-phy driver for hi3798cv200 SoC

 .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt |  36 +++
 .../boot/dts/hisilicon/hi3798cv200-poplar.dts      |  13 +
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi     |  47 ++++
 arch/arm64/configs/defconfig                       |  13 +-
 drivers/clk/hisilicon/crg-hi3798cv200.c            |  21 ++
 drivers/phy/Kconfig                                |  10 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-hisi-inno-usb2.c                   | 287 +++++++++++++++++++++
 include/dt-bindings/clock/histb-clock.h            |   9 +-
 9 files changed, 435 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
 create mode 100644 drivers/phy/phy-hisi-inno-usb2.c

-- 
1.9.1

[PATCH 1/5] clk: hisilicon: add usb2 clocks for hi3798cv200 SoC

[Jiancheng Xue]

Add usb2 clocks for hi3798cv200 SoC.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
---
 drivers/clk/hisilicon/crg-hi3798cv200.c | 21 +++++++++++++++++++++
 include/dt-bindings/clock/histb-clock.h |  9 ++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
index fc8b5bc..ed8bb5f 100644
--- a/drivers/clk/hisilicon/crg-hi3798cv200.c
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -44,6 +44,9 @@
 #define HI3798CV200_ETH_BUS0_CLK	78
 #define HI3798CV200_ETH_BUS1_CLK	79
 #define HI3798CV200_COMBPHY1_MUX	80
+#define HI3798CV200_FIXED_12M	81
+#define HI3798CV200_FIXED_48M	82
+#define HI3798CV200_FIXED_60M	83
 
 #define HI3798CV200_CRG_NR_CLKS		128
 
@@ -51,9 +54,12 @@
 	{ HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
 	{ HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
 	{ HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
+	{ HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
 	{ HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
 	{ HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
+	{ HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
 	{ HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
+	{ HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
 	{ HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
 	{ HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
 	{ HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
@@ -134,6 +140,21 @@
 	/* COMBPHY1 */
 	{ HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
 		CLK_SET_RATE_PARENT, 0x188, 8, 0, },
+	/* USB2 */
+	{ HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb",
+		CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
+	{ HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m",
+		CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
+	{ HISTB_USB2_12M_CLK, "clk_u2_12m", "12m",
+		CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
+	{ HISTB_USB2_48M_CLK, "clk_u2_48m", "48m",
+		CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
+	{ HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
+		CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
+	{ HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
+		CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
+	{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
+		CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
 };
 
 static struct hisi_clock_data *hi3798cv200_clk_register(
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index 181c0f0..067f5e5 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -53,7 +53,14 @@
 #define HISTB_ETH1_MAC_CLK		31
 #define HISTB_ETH1_MACIF_CLK		32
 #define HISTB_COMBPHY1_CLK		33
-
+#define HISTB_USB2_BUS_CLK	34
+#define HISTB_USB2_PHY_CLK	35
+#define HISTB_USB2_UTMI_CLK	36
+#define HISTB_USB2_12M_CLK	37
+#define HISTB_USB2_48M_CLK	38
+#define HISTB_USB2_OTG_UTMI_CLK	39
+#define HISTB_USB2_PHY1_REF_CLK	40
+#define HISTB_USB2_PHY2_REF_CLK	41
 
 /* clocks provided by mcu CRG */
 #define HISTB_MCE_CLK	1
-- 
1.9.1

[PATCH 1/5] clk: hisilicon: add usb2 clocks for hi3798cv200 SoC

[Jiancheng Xue]

Add usb2 clocks for hi3798cv200 SoC.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
---
 drivers/clk/hisilicon/crg-hi3798cv200.c | 21 +++++++++++++++++++++
 include/dt-bindings/clock/histb-clock.h |  9 ++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
index fc8b5bc..ed8bb5f 100644
--- a/drivers/clk/hisilicon/crg-hi3798cv200.c
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -44,6 +44,9 @@
 #define HI3798CV200_ETH_BUS0_CLK	78
 #define HI3798CV200_ETH_BUS1_CLK	79
 #define HI3798CV200_COMBPHY1_MUX	80
+#define HI3798CV200_FIXED_12M	81
+#define HI3798CV200_FIXED_48M	82
+#define HI3798CV200_FIXED_60M	83
 
 #define HI3798CV200_CRG_NR_CLKS		128
 
@@ -51,9 +54,12 @@
 	{ HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
 	{ HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
 	{ HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
+	{ HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
 	{ HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
 	{ HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
+	{ HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
 	{ HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
+	{ HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
 	{ HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
 	{ HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
 	{ HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
@@ -134,6 +140,21 @@
 	/* COMBPHY1 */
 	{ HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
 		CLK_SET_RATE_PARENT, 0x188, 8, 0, },
+	/* USB2 */
+	{ HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb",
+		CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
+	{ HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m",
+		CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
+	{ HISTB_USB2_12M_CLK, "clk_u2_12m", "12m",
+		CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
+	{ HISTB_USB2_48M_CLK, "clk_u2_48m", "48m",
+		CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
+	{ HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
+		CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
+	{ HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
+		CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
+	{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
+		CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
 };
 
 static struct hisi_clock_data *hi3798cv200_clk_register(
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index 181c0f0..067f5e5 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -53,7 +53,14 @@
 #define HISTB_ETH1_MAC_CLK		31
 #define HISTB_ETH1_MACIF_CLK		32
 #define HISTB_COMBPHY1_CLK		33
-
+#define HISTB_USB2_BUS_CLK	34
+#define HISTB_USB2_PHY_CLK	35
+#define HISTB_USB2_UTMI_CLK	36
+#define HISTB_USB2_12M_CLK	37
+#define HISTB_USB2_48M_CLK	38
+#define HISTB_USB2_OTG_UTMI_CLK	39
+#define HISTB_USB2_PHY1_REF_CLK	40
+#define HISTB_USB2_PHY2_REF_CLK	41
 
 /* clocks provided by mcu CRG */
 #define HISTB_MCE_CLK	1
-- 
1.9.1

[PATCH 1/5] clk: hisilicon: add usb2 clocks for hi3798cv200 SoC

[Jiancheng Xue]

Add usb2 clocks for hi3798cv200 SoC.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
---
 drivers/clk/hisilicon/crg-hi3798cv200.c | 21 +++++++++++++++++++++
 include/dt-bindings/clock/histb-clock.h |  9 ++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
index fc8b5bc..ed8bb5f 100644
--- a/drivers/clk/hisilicon/crg-hi3798cv200.c
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -44,6 +44,9 @@
 #define HI3798CV200_ETH_BUS0_CLK	78
 #define HI3798CV200_ETH_BUS1_CLK	79
 #define HI3798CV200_COMBPHY1_MUX	80
+#define HI3798CV200_FIXED_12M	81
+#define HI3798CV200_FIXED_48M	82
+#define HI3798CV200_FIXED_60M	83
 
 #define HI3798CV200_CRG_NR_CLKS		128
 
@@ -51,9 +54,12 @@
 	{ HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
 	{ HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
 	{ HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
+	{ HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
 	{ HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
 	{ HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
+	{ HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
 	{ HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
+	{ HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
 	{ HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
 	{ HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
 	{ HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
@@ -134,6 +140,21 @@
 	/* COMBPHY1 */
 	{ HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
 		CLK_SET_RATE_PARENT, 0x188, 8, 0, },
+	/* USB2 */
+	{ HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb",
+		CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
+	{ HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m",
+		CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
+	{ HISTB_USB2_12M_CLK, "clk_u2_12m", "12m",
+		CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
+	{ HISTB_USB2_48M_CLK, "clk_u2_48m", "48m",
+		CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
+	{ HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
+		CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
+	{ HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
+		CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
+	{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
+		CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
 };
 
 static struct hisi_clock_data *hi3798cv200_clk_register(
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index 181c0f0..067f5e5 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -53,7 +53,14 @@
 #define HISTB_ETH1_MAC_CLK		31
 #define HISTB_ETH1_MACIF_CLK		32
 #define HISTB_COMBPHY1_CLK		33
-
+#define HISTB_USB2_BUS_CLK	34
+#define HISTB_USB2_PHY_CLK	35
+#define HISTB_USB2_UTMI_CLK	36
+#define HISTB_USB2_12M_CLK	37
+#define HISTB_USB2_48M_CLK	38
+#define HISTB_USB2_OTG_UTMI_CLK	39
+#define HISTB_USB2_PHY1_REF_CLK	40
+#define HISTB_USB2_PHY2_REF_CLK	41
 
 /* clocks provided by mcu CRG */
 #define HISTB_MCE_CLK	1
-- 
1.9.1

[PATCH 2/5] dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy

[Jiancheng Xue]

Add support for hisi-inno-usb2 phy.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
---
 .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
new file mode 100644
index 0000000..21f8208
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
@@ -0,0 +1,36 @@
+HiSilicon INNO USB2 PHY
+-----------------------
+Required properties:
+- compatible: Should be one of the following strings:
+		"hisilicon,inno-usb2-phy",
+		"hisilicon,hi3798cv200-usb2-phy",
+- #phy-cells: Must be 0
+- hisilicon,peripheral-syscon: Phandle of syscon used to control phy.
+- clocks: Phandle and clock specifier pair for reference clock utmi_refclk.
+- resets: List of phandle and reset specifier pairs for each reset signal in
+reset-names.
+- reset-names: Should be "por_rst" and "test_rst". The test_rst only
+exists in some of SOCs, so it is optional.
+
+Phy node can include up to four subnodes. Each subnode represents one port.
+The required properties of port node are as follows:
+- clocks: Phandle and clock specifier pair for utmi_clock.
+- resets: List of phandle and reset specifier pairs for port reset and utmi reset.
+- reset-names: List of reset signal names. Should be "port_rst" and "utmi_rst"
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Example:
+usb_phy: phy {
+		 compatible = "hisilicon,inno_usb2_phy";
+		 #phy-cells = <0>;
+		 hisilicon,peripheral-syscon = <&peri_ctrl>;
+		 clocks = <&crg USB2_REF_CLK>;
+		 resets = <&crg 0xb4 2>;
+		 reset-names = "por_rst";
+		 port0 {
+			 clocks = <&crg USB2_UTMI0_CLK>;
+			 resets = <&crg 0xb4 5>, <&crg 0xb4 1>;
+			 reset-names = "port_rst", "utmi_rst";
+		 };
+	 };
-- 
1.9.1

[PATCH 2/5] dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy

[Jiancheng Xue]

Add support for hisi-inno-usb2 phy.

Signed-off-by: Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
 .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
new file mode 100644
index 0000000..21f8208
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
@@ -0,0 +1,36 @@
+HiSilicon INNO USB2 PHY
+-----------------------
+Required properties:
+- compatible: Should be one of the following strings:
+		"hisilicon,inno-usb2-phy",
+		"hisilicon,hi3798cv200-usb2-phy",
+- #phy-cells: Must be 0
+- hisilicon,peripheral-syscon: Phandle of syscon used to control phy.
+- clocks: Phandle and clock specifier pair for reference clock utmi_refclk.
+- resets: List of phandle and reset specifier pairs for each reset signal in
+reset-names.
+- reset-names: Should be "por_rst" and "test_rst". The test_rst only
+exists in some of SOCs, so it is optional.
+
+Phy node can include up to four subnodes. Each subnode represents one port.
+The required properties of port node are as follows:
+- clocks: Phandle and clock specifier pair for utmi_clock.
+- resets: List of phandle and reset specifier pairs for port reset and utmi reset.
+- reset-names: List of reset signal names. Should be "port_rst" and "utmi_rst"
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Example:
+usb_phy: phy {
+		 compatible = "hisilicon,inno_usb2_phy";
+		 #phy-cells = <0>;
+		 hisilicon,peripheral-syscon = <&peri_ctrl>;
+		 clocks = <&crg USB2_REF_CLK>;
+		 resets = <&crg 0xb4 2>;
+		 reset-names = "por_rst";
+		 port0 {
+			 clocks = <&crg USB2_UTMI0_CLK>;
+			 resets = <&crg 0xb4 5>, <&crg 0xb4 1>;
+			 reset-names = "port_rst", "utmi_rst";
+		 };
+	 };
-- 
1.9.1

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[PATCH 2/5] dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy

[Jiancheng Xue]

Add support for hisi-inno-usb2 phy.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
---
 .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
new file mode 100644
index 0000000..21f8208
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
@@ -0,0 +1,36 @@
+HiSilicon INNO USB2 PHY
+-----------------------
+Required properties:
+- compatible: Should be one of the following strings:
+		"hisilicon,inno-usb2-phy",
+		"hisilicon,hi3798cv200-usb2-phy",
+- #phy-cells: Must be 0
+- hisilicon,peripheral-syscon: Phandle of syscon used to control phy.
+- clocks: Phandle and clock specifier pair for reference clock utmi_refclk.
+- resets: List of phandle and reset specifier pairs for each reset signal in
+reset-names.
+- reset-names: Should be "por_rst" and "test_rst". The test_rst only
+exists in some of SOCs, so it is optional.
+
+Phy node can include up to four subnodes. Each subnode represents one port.
+The required properties of port node are as follows:
+- clocks: Phandle and clock specifier pair for utmi_clock.
+- resets: List of phandle and reset specifier pairs for port reset and utmi reset.
+- reset-names: List of reset signal names. Should be "port_rst" and "utmi_rst"
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Example:
+usb_phy: phy {
+		 compatible = "hisilicon,inno_usb2_phy";
+		 #phy-cells = <0>;
+		 hisilicon,peripheral-syscon = <&peri_ctrl>;
+		 clocks = <&crg USB2_REF_CLK>;
+		 resets = <&crg 0xb4 2>;
+		 reset-names = "por_rst";
+		 port0 {
+			 clocks = <&crg USB2_UTMI0_CLK>;
+			 resets = <&crg 0xb4 5>, <&crg 0xb4 1>;
+			 reset-names = "port_rst", "utmi_rst";
+		 };
+	 };
-- 
1.9.1

[PATCH 3/5] phy: add inno-usb2-phy driver for hi3798cv200 SoC

[Jiancheng Xue]

From: Pengcheng Li <lpc.li@hisilicon.com>

Add inno-usb2-phy driver for hi3798cv200 SoC.

Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
---
 drivers/phy/Kconfig              |  10 ++
 drivers/phy/Makefile             |   1 +
 drivers/phy/phy-hisi-inno-usb2.c | 287 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 298 insertions(+)
 create mode 100644 drivers/phy/phy-hisi-inno-usb2.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afaf7b6..f86b9b7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -225,6 +225,16 @@ config PHY_EXYNOS5250_SATA
 	  SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host
 	  port to accept one SATA device.
 
+config PHY_HISI_INNO_USB2
+	tristate "HiSilicon INNO USB2 PHY support"
+	depends on (ARCH_HISI) || COMPILE_TEST
+	select GENERIC_PHY
+	select MFD_SYSCON
+	help
+	  Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
+	  USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It supports one
+	  USB host port to accept one USB device.
+
 config PHY_HIX5HD2_SATA
 	tristate "HIX5HD2 SATA PHY Driver"
 	depends on ARCH_HIX5HD2 && OF && HAS_IOMEM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f8047b4..a275547 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
 obj-$(CONFIG_PHY_EXYNOS5250_SATA)	+= phy-exynos5250-sata.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA)		+= phy-hix5hd2-sata.o
 obj-$(CONFIG_PHY_HI6220_USB)		+= phy-hi6220-usb.o
+obj-$(CONFIG_PHY_HISI_INNO_USB2)	+= phy-hisi-inno-usb2.o
 obj-$(CONFIG_PHY_MT65XX_USB3)		+= phy-mt65xx-usb3.o
 obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
diff --git a/drivers/phy/phy-hisi-inno-usb2.c b/drivers/phy/phy-hisi-inno-usb2.c
new file mode 100644
index 0000000..582c500
--- /dev/null
+++ b/drivers/phy/phy-hisi-inno-usb2.c
@@ -0,0 +1,287 @@
+/*
+ * HiSilicon INNO USB2 PHY Driver.
+ *
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define	MAX_PORTS	4
+#define REF_CLK_STABLE_TIME	100	/*unit:us*/
+#define UTMI_CLK_STABLE_TIME	200	/*unit:us*/
+#define UTMI_RST_COMPLETE_TIME	200	/*unit:us*/
+#define PORT_RST_COMPLETE_TIME	2	/*unit:ms*/
+#define TEST_RST_COMPLETE_TIME	100	/*unit:us*/
+#define POR_RST_COMPLETE_TIME	300	/*unit:us*/
+
+
+struct  hisi_inno_phy_port {
+	struct clk *utmi_clk;
+	struct reset_control *port_rst;
+	struct reset_control *utmi_rst;
+};
+
+struct hisi_inno_phy_priv {
+	struct regmap *reg_peri;
+	struct clk *ref_clk;
+	struct reset_control *test_rst;
+	struct reset_control *por_rst;
+	const struct reg_sequence *reg_seq;
+	u32	reg_num;
+	struct  hisi_inno_phy_port *ports;
+	u8	port_num;
+};
+
+#define HI3798CV200_PERI_USB0	0x120
+static const struct reg_sequence hi3798cv200_reg_seq[] = {
+	{ HI3798CV200_PERI_USB0, 0x00a00604, },
+	{ HI3798CV200_PERI_USB0, 0x00e00604, },
+	{ HI3798CV200_PERI_USB0, 0x00a00604, 1000 },
+};
+
+static int hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
+{
+	return regmap_multi_reg_write_bypassed(priv->reg_peri,
+				priv->reg_seq, priv->reg_num);
+}
+
+static int hisi_inno_port_init(struct hisi_inno_phy_port *port)
+{
+	int ret;
+
+	reset_control_deassert(port->port_rst);
+	msleep(PORT_RST_COMPLETE_TIME);
+
+	ret = clk_prepare_enable(port->utmi_clk);
+	if (ret)
+		return ret;
+	udelay(UTMI_CLK_STABLE_TIME);
+
+	reset_control_deassert(port->utmi_rst);
+	udelay(UTMI_RST_COMPLETE_TIME);
+
+	return 0;
+}
+
+static int hisi_inno_phy_init(struct phy *phy)
+{
+	struct hisi_inno_phy_priv *priv = phy_get_drvdata(phy);
+	int ret, port;
+
+	ret = clk_prepare_enable(priv->ref_clk);
+	if (ret)
+		return ret;
+	udelay(REF_CLK_STABLE_TIME);
+
+	if (priv->test_rst) {
+		reset_control_deassert(priv->test_rst);
+		udelay(TEST_RST_COMPLETE_TIME);
+	}
+
+	reset_control_deassert(priv->por_rst);
+	udelay(POR_RST_COMPLETE_TIME);
+
+	/* config phy clk and phy eye diagram */
+	ret = hisi_inno_phy_setup(priv);
+	if (ret)
+		goto err_disable_ref_clk;
+
+	for (port = 0; port < priv->port_num; port++) {
+		ret = hisi_inno_port_init(&priv->ports[port]);
+		if (ret)
+			goto err_disable_clks;
+	}
+
+	return 0;
+
+err_disable_clks:
+	while (--port >= 0)
+		clk_disable_unprepare(priv->ports[port].utmi_clk);
+err_disable_ref_clk:
+	clk_disable_unprepare(priv->ref_clk);
+
+	return ret;
+}
+
+static void hisi_inno_phy_disable(struct phy *phy)
+{
+	struct hisi_inno_phy_priv *priv = phy_get_drvdata(phy);
+	int i;
+
+	for (i = 0; i < priv->port_num; i++)
+		clk_disable_unprepare(priv->ports[i].utmi_clk);
+
+	clk_disable_unprepare(priv->ref_clk);
+}
+
+static int hisi_inno_phy_of_get_ports(struct device *dev,
+					struct  hisi_inno_phy_priv *priv)
+{
+	struct device_node *node = dev->of_node;
+	struct device_node *child;
+	int port = 0;
+	int ret;
+
+	priv->port_num = of_get_child_count(node);
+	if (priv->port_num > MAX_PORTS) {
+		dev_err(dev, "too many ports : %d (max = %d)\n",
+				priv->port_num, MAX_PORTS);
+		return -EINVAL;
+	}
+
+	priv->ports = devm_kcalloc(dev, priv->port_num,
+				sizeof(struct hisi_inno_phy_port), GFP_KERNEL);
+	if (!priv->ports)
+		return -ENOMEM;
+
+	for_each_child_of_node(node, child) {
+		struct hisi_inno_phy_port *phy_port = &priv->ports[port];
+
+		phy_port->utmi_clk = devm_get_clk_from_child(dev, child, NULL);
+		if (IS_ERR(phy_port->utmi_clk)) {
+			ret = PTR_ERR(phy_port->utmi_clk);
+			goto fail;
+		}
+
+		phy_port->port_rst = of_reset_control_get_exclusive(child, "port_rst");
+		if (IS_ERR(phy_port->port_rst)) {
+			ret = PTR_ERR(phy_port->port_rst);
+			goto fail;
+		}
+
+		phy_port->utmi_rst = of_reset_control_get_exclusive(child, "utmi_rst");
+		if (IS_ERR(phy_port->utmi_rst)) {
+			ret = PTR_ERR(phy_port->utmi_rst);
+			reset_control_put(phy_port->port_rst);
+			goto fail;
+		}
+		port++;
+	}
+
+	return 0;
+
+fail:
+	while (--port >= 0) {
+		struct hisi_inno_phy_port *phy_port = &priv->ports[port];
+
+		reset_control_put(phy_port->utmi_rst);
+		reset_control_put(phy_port->port_rst);
+		clk_put(phy_port->utmi_clk);
+	}
+	of_node_put(child);
+
+	return ret;
+}
+
+static int hisi_inno_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct phy *phy;
+	struct hisi_inno_phy_priv *priv;
+	struct device_node *node = dev->of_node;
+	int ret = 0;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	if (of_device_is_compatible(node, "hisilicon,hi3798cv200-usb2-phy")) {
+		priv->reg_seq = hi3798cv200_reg_seq;
+		priv->reg_num = sizeof(hi3798cv200_reg_seq)
+				/ sizeof(struct reg_sequence);
+	}
+
+	priv->reg_peri = syscon_regmap_lookup_by_phandle(node,
+			"hisilicon,peripheral-syscon");
+	if (IS_ERR(priv->reg_peri)) {
+		dev_err(dev, "no hisilicon,peripheral-syscon\n");
+		return PTR_ERR(priv->reg_peri);
+	}
+
+	priv->ref_clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->ref_clk))
+		return PTR_ERR(priv->ref_clk);
+
+	priv->por_rst = devm_reset_control_get_exclusive(dev, "por_rst");
+	if (IS_ERR(priv->por_rst))
+		return PTR_ERR(priv->por_rst);
+
+	priv->test_rst = devm_reset_control_get_optional_exclusive(dev, "test_rst");
+	if (IS_ERR(priv->test_rst))
+		return PTR_ERR(priv->test_rst);
+
+	ret = hisi_inno_phy_of_get_ports(dev, priv);
+	if (ret)
+		return ret;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, phy);
+	phy_set_drvdata(phy, priv);
+
+	return hisi_inno_phy_init(phy);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int hisi_inno_phy_suspend(struct device *dev)
+{
+	struct phy *phy = dev_get_drvdata(dev);
+
+	hisi_inno_phy_disable(phy);
+
+	return 0;
+}
+
+static int hisi_inno_phy_resume(struct device *dev)
+{
+	struct phy *phy = dev_get_drvdata(dev);
+
+	return hisi_inno_phy_init(phy);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops hisi_inno_phy_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(hisi_inno_phy_suspend, hisi_inno_phy_resume)
+};
+
+static const struct of_device_id hisi_inno_phy_of_match[] = {
+	{.compatible = "hisilicon,inno-usb2-phy",},
+	{.compatible = "hisilicon,hi3798cv200-usb2-phy",},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);
+
+static struct platform_driver hisi_inno_phy_driver = {
+	.probe	= hisi_inno_phy_probe,
+	.driver = {
+		.name	= "hisi-inno-phy",
+		.of_match_table	= hisi_inno_phy_of_match,
+		.pm    = &hisi_inno_phy_pm_ops,
+	}
+};
+module_platform_driver(hisi_inno_phy_driver);
+
+MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

[PATCH 3/5] phy: add inno-usb2-phy driver for hi3798cv200 SoC

[Jiancheng Xue]

From: Pengcheng Li <lpc.li@hisilicon.com>

Add inno-usb2-phy driver for hi3798cv200 SoC.

Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
---
 drivers/phy/Kconfig              |  10 ++
 drivers/phy/Makefile             |   1 +
 drivers/phy/phy-hisi-inno-usb2.c | 287 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 298 insertions(+)
 create mode 100644 drivers/phy/phy-hisi-inno-usb2.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afaf7b6..f86b9b7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -225,6 +225,16 @@ config PHY_EXYNOS5250_SATA
 	  SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host
 	  port to accept one SATA device.
 
+config PHY_HISI_INNO_USB2
+	tristate "HiSilicon INNO USB2 PHY support"
+	depends on (ARCH_HISI) || COMPILE_TEST
+	select GENERIC_PHY
+	select MFD_SYSCON
+	help
+	  Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
+	  USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It supports one
+	  USB host port to accept one USB device.
+
 config PHY_HIX5HD2_SATA
 	tristate "HIX5HD2 SATA PHY Driver"
 	depends on ARCH_HIX5HD2 && OF && HAS_IOMEM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f8047b4..a275547 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
 obj-$(CONFIG_PHY_EXYNOS5250_SATA)	+= phy-exynos5250-sata.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA)		+= phy-hix5hd2-sata.o
 obj-$(CONFIG_PHY_HI6220_USB)		+= phy-hi6220-usb.o
+obj-$(CONFIG_PHY_HISI_INNO_USB2)	+= phy-hisi-inno-usb2.o
 obj-$(CONFIG_PHY_MT65XX_USB3)		+= phy-mt65xx-usb3.o
 obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
diff --git a/drivers/phy/phy-hisi-inno-usb2.c b/drivers/phy/phy-hisi-inno-usb2.c
new file mode 100644
index 0000000..582c500
--- /dev/null
+++ b/drivers/phy/phy-hisi-inno-usb2.c
@@ -0,0 +1,287 @@
+/*
+ * HiSilicon INNO USB2 PHY Driver.
+ *
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define	MAX_PORTS	4
+#define REF_CLK_STABLE_TIME	100	/*unit:us*/
+#define UTMI_CLK_STABLE_TIME	200	/*unit:us*/
+#define UTMI_RST_COMPLETE_TIME	200	/*unit:us*/
+#define PORT_RST_COMPLETE_TIME	2	/*unit:ms*/
+#define TEST_RST_COMPLETE_TIME	100	/*unit:us*/
+#define POR_RST_COMPLETE_TIME	300	/*unit:us*/
+
+
+struct  hisi_inno_phy_port {
+	struct clk *utmi_clk;
+	struct reset_control *port_rst;
+	struct reset_control *utmi_rst;
+};
+
+struct hisi_inno_phy_priv {
+	struct regmap *reg_peri;
+	struct clk *ref_clk;
+	struct reset_control *test_rst;
+	struct reset_control *por_rst;
+	const struct reg_sequence *reg_seq;
+	u32	reg_num;
+	struct  hisi_inno_phy_port *ports;
+	u8	port_num;
+};
+
+#define HI3798CV200_PERI_USB0	0x120
+static const struct reg_sequence hi3798cv200_reg_seq[] = {
+	{ HI3798CV200_PERI_USB0, 0x00a00604, },
+	{ HI3798CV200_PERI_USB0, 0x00e00604, },
+	{ HI3798CV200_PERI_USB0, 0x00a00604, 1000 },
+};
+
+static int hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
+{
+	return regmap_multi_reg_write_bypassed(priv->reg_peri,
+				priv->reg_seq, priv->reg_num);
+}
+
+static int hisi_inno_port_init(struct hisi_inno_phy_port *port)
+{
+	int ret;
+
+	reset_control_deassert(port->port_rst);
+	msleep(PORT_RST_COMPLETE_TIME);
+
+	ret = clk_prepare_enable(port->utmi_clk);
+	if (ret)
+		return ret;
+	udelay(UTMI_CLK_STABLE_TIME);
+
+	reset_control_deassert(port->utmi_rst);
+	udelay(UTMI_RST_COMPLETE_TIME);
+
+	return 0;
+}
+
+static int hisi_inno_phy_init(struct phy *phy)
+{
+	struct hisi_inno_phy_priv *priv = phy_get_drvdata(phy);
+	int ret, port;
+
+	ret = clk_prepare_enable(priv->ref_clk);
+	if (ret)
+		return ret;
+	udelay(REF_CLK_STABLE_TIME);
+
+	if (priv->test_rst) {
+		reset_control_deassert(priv->test_rst);
+		udelay(TEST_RST_COMPLETE_TIME);
+	}
+
+	reset_control_deassert(priv->por_rst);
+	udelay(POR_RST_COMPLETE_TIME);
+
+	/* config phy clk and phy eye diagram */
+	ret = hisi_inno_phy_setup(priv);
+	if (ret)
+		goto err_disable_ref_clk;
+
+	for (port = 0; port < priv->port_num; port++) {
+		ret = hisi_inno_port_init(&priv->ports[port]);
+		if (ret)
+			goto err_disable_clks;
+	}
+
+	return 0;
+
+err_disable_clks:
+	while (--port >= 0)
+		clk_disable_unprepare(priv->ports[port].utmi_clk);
+err_disable_ref_clk:
+	clk_disable_unprepare(priv->ref_clk);
+
+	return ret;
+}
+
+static void hisi_inno_phy_disable(struct phy *phy)
+{
+	struct hisi_inno_phy_priv *priv = phy_get_drvdata(phy);
+	int i;
+
+	for (i = 0; i < priv->port_num; i++)
+		clk_disable_unprepare(priv->ports[i].utmi_clk);
+
+	clk_disable_unprepare(priv->ref_clk);
+}
+
+static int hisi_inno_phy_of_get_ports(struct device *dev,
+					struct  hisi_inno_phy_priv *priv)
+{
+	struct device_node *node = dev->of_node;
+	struct device_node *child;
+	int port = 0;
+	int ret;
+
+	priv->port_num = of_get_child_count(node);
+	if (priv->port_num > MAX_PORTS) {
+		dev_err(dev, "too many ports : %d (max = %d)\n",
+				priv->port_num, MAX_PORTS);
+		return -EINVAL;
+	}
+
+	priv->ports = devm_kcalloc(dev, priv->port_num,
+				sizeof(struct hisi_inno_phy_port), GFP_KERNEL);
+	if (!priv->ports)
+		return -ENOMEM;
+
+	for_each_child_of_node(node, child) {
+		struct hisi_inno_phy_port *phy_port = &priv->ports[port];
+
+		phy_port->utmi_clk = devm_get_clk_from_child(dev, child, NULL);
+		if (IS_ERR(phy_port->utmi_clk)) {
+			ret = PTR_ERR(phy_port->utmi_clk);
+			goto fail;
+		}
+
+		phy_port->port_rst = of_reset_control_get_exclusive(child, "port_rst");
+		if (IS_ERR(phy_port->port_rst)) {
+			ret = PTR_ERR(phy_port->port_rst);
+			goto fail;
+		}
+
+		phy_port->utmi_rst = of_reset_control_get_exclusive(child, "utmi_rst");
+		if (IS_ERR(phy_port->utmi_rst)) {
+			ret = PTR_ERR(phy_port->utmi_rst);
+			reset_control_put(phy_port->port_rst);
+			goto fail;
+		}
+		port++;
+	}
+
+	return 0;
+
+fail:
+	while (--port >= 0) {
+		struct hisi_inno_phy_port *phy_port = &priv->ports[port];
+
+		reset_control_put(phy_port->utmi_rst);
+		reset_control_put(phy_port->port_rst);
+		clk_put(phy_port->utmi_clk);
+	}
+	of_node_put(child);
+
+	return ret;
+}
+
+static int hisi_inno_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct phy *phy;
+	struct hisi_inno_phy_priv *priv;
+	struct device_node *node = dev->of_node;
+	int ret = 0;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	if (of_device_is_compatible(node, "hisilicon,hi3798cv200-usb2-phy")) {
+		priv->reg_seq = hi3798cv200_reg_seq;
+		priv->reg_num = sizeof(hi3798cv200_reg_seq)
+				/ sizeof(struct reg_sequence);
+	}
+
+	priv->reg_peri = syscon_regmap_lookup_by_phandle(node,
+			"hisilicon,peripheral-syscon");
+	if (IS_ERR(priv->reg_peri)) {
+		dev_err(dev, "no hisilicon,peripheral-syscon\n");
+		return PTR_ERR(priv->reg_peri);
+	}
+
+	priv->ref_clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->ref_clk))
+		return PTR_ERR(priv->ref_clk);
+
+	priv->por_rst = devm_reset_control_get_exclusive(dev, "por_rst");
+	if (IS_ERR(priv->por_rst))
+		return PTR_ERR(priv->por_rst);
+
+	priv->test_rst = devm_reset_control_get_optional_exclusive(dev, "test_rst");
+	if (IS_ERR(priv->test_rst))
+		return PTR_ERR(priv->test_rst);
+
+	ret = hisi_inno_phy_of_get_ports(dev, priv);
+	if (ret)
+		return ret;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, phy);
+	phy_set_drvdata(phy, priv);
+
+	return hisi_inno_phy_init(phy);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int hisi_inno_phy_suspend(struct device *dev)
+{
+	struct phy *phy = dev_get_drvdata(dev);
+
+	hisi_inno_phy_disable(phy);
+
+	return 0;
+}
+
+static int hisi_inno_phy_resume(struct device *dev)
+{
+	struct phy *phy = dev_get_drvdata(dev);
+
+	return hisi_inno_phy_init(phy);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops hisi_inno_phy_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(hisi_inno_phy_suspend, hisi_inno_phy_resume)
+};
+
+static const struct of_device_id hisi_inno_phy_of_match[] = {
+	{.compatible = "hisilicon,inno-usb2-phy",},
+	{.compatible = "hisilicon,hi3798cv200-usb2-phy",},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);
+
+static struct platform_driver hisi_inno_phy_driver = {
+	.probe	= hisi_inno_phy_probe,
+	.driver = {
+		.name	= "hisi-inno-phy",
+		.of_match_table	= hisi_inno_phy_of_match,
+		.pm    = &hisi_inno_phy_pm_ops,
+	}
+};
+module_platform_driver(hisi_inno_phy_driver);
+
+MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

[PATCH 3/5] phy: add inno-usb2-phy driver for hi3798cv200 SoC

[Jiancheng Xue]

From: Pengcheng Li <lpc.li@hisilicon.com>

Add inno-usb2-phy driver for hi3798cv200 SoC.

Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
---
 drivers/phy/Kconfig              |  10 ++
 drivers/phy/Makefile             |   1 +
 drivers/phy/phy-hisi-inno-usb2.c | 287 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 298 insertions(+)
 create mode 100644 drivers/phy/phy-hisi-inno-usb2.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afaf7b6..f86b9b7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -225,6 +225,16 @@ config PHY_EXYNOS5250_SATA
 	  SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host
 	  port to accept one SATA device.
 
+config PHY_HISI_INNO_USB2
+	tristate "HiSilicon INNO USB2 PHY support"
+	depends on (ARCH_HISI) || COMPILE_TEST
+	select GENERIC_PHY
+	select MFD_SYSCON
+	help
+	  Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
+	  USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It supports one
+	  USB host port to accept one USB device.
+
 config PHY_HIX5HD2_SATA
 	tristate "HIX5HD2 SATA PHY Driver"
 	depends on ARCH_HIX5HD2 && OF && HAS_IOMEM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f8047b4..a275547 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
 obj-$(CONFIG_PHY_EXYNOS5250_SATA)	+= phy-exynos5250-sata.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA)		+= phy-hix5hd2-sata.o
 obj-$(CONFIG_PHY_HI6220_USB)		+= phy-hi6220-usb.o
+obj-$(CONFIG_PHY_HISI_INNO_USB2)	+= phy-hisi-inno-usb2.o
 obj-$(CONFIG_PHY_MT65XX_USB3)		+= phy-mt65xx-usb3.o
 obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
diff --git a/drivers/phy/phy-hisi-inno-usb2.c b/drivers/phy/phy-hisi-inno-usb2.c
new file mode 100644
index 0000000..582c500
--- /dev/null
+++ b/drivers/phy/phy-hisi-inno-usb2.c
@@ -0,0 +1,287 @@
+/*
+ * HiSilicon INNO USB2 PHY Driver.
+ *
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define	MAX_PORTS	4
+#define REF_CLK_STABLE_TIME	100	/*unit:us*/
+#define UTMI_CLK_STABLE_TIME	200	/*unit:us*/
+#define UTMI_RST_COMPLETE_TIME	200	/*unit:us*/
+#define PORT_RST_COMPLETE_TIME	2	/*unit:ms*/
+#define TEST_RST_COMPLETE_TIME	100	/*unit:us*/
+#define POR_RST_COMPLETE_TIME	300	/*unit:us*/
+
+
+struct  hisi_inno_phy_port {
+	struct clk *utmi_clk;
+	struct reset_control *port_rst;
+	struct reset_control *utmi_rst;
+};
+
+struct hisi_inno_phy_priv {
+	struct regmap *reg_peri;
+	struct clk *ref_clk;
+	struct reset_control *test_rst;
+	struct reset_control *por_rst;
+	const struct reg_sequence *reg_seq;
+	u32	reg_num;
+	struct  hisi_inno_phy_port *ports;
+	u8	port_num;
+};
+
+#define HI3798CV200_PERI_USB0	0x120
+static const struct reg_sequence hi3798cv200_reg_seq[] = {
+	{ HI3798CV200_PERI_USB0, 0x00a00604, },
+	{ HI3798CV200_PERI_USB0, 0x00e00604, },
+	{ HI3798CV200_PERI_USB0, 0x00a00604, 1000 },
+};
+
+static int hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
+{
+	return regmap_multi_reg_write_bypassed(priv->reg_peri,
+				priv->reg_seq, priv->reg_num);
+}
+
+static int hisi_inno_port_init(struct hisi_inno_phy_port *port)
+{
+	int ret;
+
+	reset_control_deassert(port->port_rst);
+	msleep(PORT_RST_COMPLETE_TIME);
+
+	ret = clk_prepare_enable(port->utmi_clk);
+	if (ret)
+		return ret;
+	udelay(UTMI_CLK_STABLE_TIME);
+
+	reset_control_deassert(port->utmi_rst);
+	udelay(UTMI_RST_COMPLETE_TIME);
+
+	return 0;
+}
+
+static int hisi_inno_phy_init(struct phy *phy)
+{
+	struct hisi_inno_phy_priv *priv = phy_get_drvdata(phy);
+	int ret, port;
+
+	ret = clk_prepare_enable(priv->ref_clk);
+	if (ret)
+		return ret;
+	udelay(REF_CLK_STABLE_TIME);
+
+	if (priv->test_rst) {
+		reset_control_deassert(priv->test_rst);
+		udelay(TEST_RST_COMPLETE_TIME);
+	}
+
+	reset_control_deassert(priv->por_rst);
+	udelay(POR_RST_COMPLETE_TIME);
+
+	/* config phy clk and phy eye diagram */
+	ret = hisi_inno_phy_setup(priv);
+	if (ret)
+		goto err_disable_ref_clk;
+
+	for (port = 0; port < priv->port_num; port++) {
+		ret = hisi_inno_port_init(&priv->ports[port]);
+		if (ret)
+			goto err_disable_clks;
+	}
+
+	return 0;
+
+err_disable_clks:
+	while (--port >= 0)
+		clk_disable_unprepare(priv->ports[port].utmi_clk);
+err_disable_ref_clk:
+	clk_disable_unprepare(priv->ref_clk);
+
+	return ret;
+}
+
+static void hisi_inno_phy_disable(struct phy *phy)
+{
+	struct hisi_inno_phy_priv *priv = phy_get_drvdata(phy);
+	int i;
+
+	for (i = 0; i < priv->port_num; i++)
+		clk_disable_unprepare(priv->ports[i].utmi_clk);
+
+	clk_disable_unprepare(priv->ref_clk);
+}
+
+static int hisi_inno_phy_of_get_ports(struct device *dev,
+					struct  hisi_inno_phy_priv *priv)
+{
+	struct device_node *node = dev->of_node;
+	struct device_node *child;
+	int port = 0;
+	int ret;
+
+	priv->port_num = of_get_child_count(node);
+	if (priv->port_num > MAX_PORTS) {
+		dev_err(dev, "too many ports : %d (max = %d)\n",
+				priv->port_num, MAX_PORTS);
+		return -EINVAL;
+	}
+
+	priv->ports = devm_kcalloc(dev, priv->port_num,
+				sizeof(struct hisi_inno_phy_port), GFP_KERNEL);
+	if (!priv->ports)
+		return -ENOMEM;
+
+	for_each_child_of_node(node, child) {
+		struct hisi_inno_phy_port *phy_port = &priv->ports[port];
+
+		phy_port->utmi_clk = devm_get_clk_from_child(dev, child, NULL);
+		if (IS_ERR(phy_port->utmi_clk)) {
+			ret = PTR_ERR(phy_port->utmi_clk);
+			goto fail;
+		}
+
+		phy_port->port_rst = of_reset_control_get_exclusive(child, "port_rst");
+		if (IS_ERR(phy_port->port_rst)) {
+			ret = PTR_ERR(phy_port->port_rst);
+			goto fail;
+		}
+
+		phy_port->utmi_rst = of_reset_control_get_exclusive(child, "utmi_rst");
+		if (IS_ERR(phy_port->utmi_rst)) {
+			ret = PTR_ERR(phy_port->utmi_rst);
+			reset_control_put(phy_port->port_rst);
+			goto fail;
+		}
+		port++;
+	}
+
+	return 0;
+
+fail:
+	while (--port >= 0) {
+		struct hisi_inno_phy_port *phy_port = &priv->ports[port];
+
+		reset_control_put(phy_port->utmi_rst);
+		reset_control_put(phy_port->port_rst);
+		clk_put(phy_port->utmi_clk);
+	}
+	of_node_put(child);
+
+	return ret;
+}
+
+static int hisi_inno_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct phy *phy;
+	struct hisi_inno_phy_priv *priv;
+	struct device_node *node = dev->of_node;
+	int ret = 0;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	if (of_device_is_compatible(node, "hisilicon,hi3798cv200-usb2-phy")) {
+		priv->reg_seq = hi3798cv200_reg_seq;
+		priv->reg_num = sizeof(hi3798cv200_reg_seq)
+				/ sizeof(struct reg_sequence);
+	}
+
+	priv->reg_peri = syscon_regmap_lookup_by_phandle(node,
+			"hisilicon,peripheral-syscon");
+	if (IS_ERR(priv->reg_peri)) {
+		dev_err(dev, "no hisilicon,peripheral-syscon\n");
+		return PTR_ERR(priv->reg_peri);
+	}
+
+	priv->ref_clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->ref_clk))
+		return PTR_ERR(priv->ref_clk);
+
+	priv->por_rst = devm_reset_control_get_exclusive(dev, "por_rst");
+	if (IS_ERR(priv->por_rst))
+		return PTR_ERR(priv->por_rst);
+
+	priv->test_rst = devm_reset_control_get_optional_exclusive(dev, "test_rst");
+	if (IS_ERR(priv->test_rst))
+		return PTR_ERR(priv->test_rst);
+
+	ret = hisi_inno_phy_of_get_ports(dev, priv);
+	if (ret)
+		return ret;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, phy);
+	phy_set_drvdata(phy, priv);
+
+	return hisi_inno_phy_init(phy);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int hisi_inno_phy_suspend(struct device *dev)
+{
+	struct phy *phy = dev_get_drvdata(dev);
+
+	hisi_inno_phy_disable(phy);
+
+	return 0;
+}
+
+static int hisi_inno_phy_resume(struct device *dev)
+{
+	struct phy *phy = dev_get_drvdata(dev);
+
+	return hisi_inno_phy_init(phy);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops hisi_inno_phy_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(hisi_inno_phy_suspend, hisi_inno_phy_resume)
+};
+
+static const struct of_device_id hisi_inno_phy_of_match[] = {
+	{.compatible = "hisilicon,inno-usb2-phy",},
+	{.compatible = "hisilicon,hi3798cv200-usb2-phy",},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);
+
+static struct platform_driver hisi_inno_phy_driver = {
+	.probe	= hisi_inno_phy_probe,
+	.driver = {
+		.name	= "hisi-inno-phy",
+		.of_match_table	= hisi_inno_phy_of_match,
+		.pm    = &hisi_inno_phy_pm_ops,
+	}
+};
+module_platform_driver(hisi_inno_phy_driver);
+
+MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

[PATCH 4/5] arm64: dts: hisilicon: add usb2 controller and phy nodes for poplar board.

[Jiancheng Xue]

Add usb2 controller and phy nodes for poplar board.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
---
 .../boot/dts/hisilicon/hi3798cv200-poplar.dts      | 13 ++++++
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi     | 47 ++++++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
index 684fa09..40db803 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
@@ -64,6 +64,10 @@
 	};
 };
 
+&ehci {
+	status = "okay";
+};
+
 &gmac1 {
 	status = "okay";
 	#address-cells = <1>;
@@ -147,6 +151,10 @@
 	status = "okay";
 };
 
+&ohci {
+	status = "okay";
+};
+
 &spi0 {
 	status = "okay";
 	label = "LS-SPI0";
@@ -161,3 +169,8 @@
 	label = "LS-UART0";
 };
 /* No optional LS-UART1 on Low Speed Expansion Connector. */
+
+&usb2_phy1 {
+	status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 75865f8a..422aeaf 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -106,6 +106,11 @@
 			#reset-cells = <2>;
 		};
 
+		peri_ctrl: system-controller@8a20000 {
+			compatible = "syscon";
+			reg = <0x8a20000 0x1000>;
+		};
+
 		uart0: serial@8b00000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x8b00000 0x1000>;
@@ -407,5 +412,47 @@
 			clocks = <&sysctrl HISTB_IR_CLK>;
 			status = "disabled";
 		};
+
+		ehci: ehci@0x9890000 {
+			compatible = "generic-ehci";
+			reg = <0x9890000 0x10000>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_USB2_BUS_CLK>,
+				 <&crg HISTB_USB2_PHY_CLK>;
+			clock-names = "ehci_system", "phy";
+			resets = <&crg 0xb8 12>,
+				 <&crg 0xb8 16>;
+			reset-names = "bus", "phy";
+			status = "disabled";
+		};
+
+		ohci: ohci@0x9880000 {
+			compatible = "generic-ohci";
+			reg = <0x9880000 0x10000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_USB2_BUS_CLK>,
+				 <&crg HISTB_USB2_12M_CLK>,
+				 <&crg HISTB_USB2_48M_CLK>;
+			clock-names = "ahb_biu", "clk12", "clk48";
+			resets = <&crg 0xb8 12>;
+			reset-names = "bus";
+			status = "disabled";
+		};
+
+		usb2_phy1: usb-phy@1 {
+			compatible = "hisilicon,hi3798cv200-usb2-phy";
+			#phy-cells = <0>;
+			hisilicon,peripheral-syscon = <&peri_ctrl>;
+			clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+			resets = <&crg 0xbc 4>;
+			reset-names = "por_rst";
+			status = "disabled";
+
+			usb2_port1: port@1 {
+				clocks = <&crg HISTB_USB2_UTMI_CLK>;
+				resets = <&crg 0xbc 9>, <&crg 0xb8 13>;
+				reset-names = "port_rst", "utmi_rst";
+			};
+		};
 	};
 };
-- 
1.9.1

[PATCH 4/5] arm64: dts: hisilicon: add usb2 controller and phy nodes for poplar board.

[Jiancheng Xue]

Add usb2 controller and phy nodes for poplar board.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
---
 .../boot/dts/hisilicon/hi3798cv200-poplar.dts      | 13 ++++++
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi     | 47 ++++++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
index 684fa09..40db803 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
@@ -64,6 +64,10 @@
 	};
 };
 
+&ehci {
+	status = "okay";
+};
+
 &gmac1 {
 	status = "okay";
 	#address-cells = <1>;
@@ -147,6 +151,10 @@
 	status = "okay";
 };
 
+&ohci {
+	status = "okay";
+};
+
 &spi0 {
 	status = "okay";
 	label = "LS-SPI0";
@@ -161,3 +169,8 @@
 	label = "LS-UART0";
 };
 /* No optional LS-UART1 on Low Speed Expansion Connector. */
+
+&usb2_phy1 {
+	status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 75865f8a..422aeaf 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -106,6 +106,11 @@
 			#reset-cells = <2>;
 		};
 
+		peri_ctrl: system-controller@8a20000 {
+			compatible = "syscon";
+			reg = <0x8a20000 0x1000>;
+		};
+
 		uart0: serial@8b00000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x8b00000 0x1000>;
@@ -407,5 +412,47 @@
 			clocks = <&sysctrl HISTB_IR_CLK>;
 			status = "disabled";
 		};
+
+		ehci: ehci@0x9890000 {
+			compatible = "generic-ehci";
+			reg = <0x9890000 0x10000>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_USB2_BUS_CLK>,
+				 <&crg HISTB_USB2_PHY_CLK>;
+			clock-names = "ehci_system", "phy";
+			resets = <&crg 0xb8 12>,
+				 <&crg 0xb8 16>;
+			reset-names = "bus", "phy";
+			status = "disabled";
+		};
+
+		ohci: ohci@0x9880000 {
+			compatible = "generic-ohci";
+			reg = <0x9880000 0x10000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_USB2_BUS_CLK>,
+				 <&crg HISTB_USB2_12M_CLK>,
+				 <&crg HISTB_USB2_48M_CLK>;
+			clock-names = "ahb_biu", "clk12", "clk48";
+			resets = <&crg 0xb8 12>;
+			reset-names = "bus";
+			status = "disabled";
+		};
+
+		usb2_phy1: usb-phy@1 {
+			compatible = "hisilicon,hi3798cv200-usb2-phy";
+			#phy-cells = <0>;
+			hisilicon,peripheral-syscon = <&peri_ctrl>;
+			clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+			resets = <&crg 0xbc 4>;
+			reset-names = "por_rst";
+			status = "disabled";
+
+			usb2_port1: port@1 {
+				clocks = <&crg HISTB_USB2_UTMI_CLK>;
+				resets = <&crg 0xbc 9>, <&crg 0xb8 13>;
+				reset-names = "port_rst", "utmi_rst";
+			};
+		};
 	};
 };
-- 
1.9.1

[PATCH 4/5] arm64: dts: hisilicon: add usb2 controller and phy nodes for poplar board.

[Jiancheng Xue]

Add usb2 controller and phy nodes for poplar board.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
---
 .../boot/dts/hisilicon/hi3798cv200-poplar.dts      | 13 ++++++
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi     | 47 ++++++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
index 684fa09..40db803 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
@@ -64,6 +64,10 @@
 	};
 };
 
+&ehci {
+	status = "okay";
+};
+
 &gmac1 {
 	status = "okay";
 	#address-cells = <1>;
@@ -147,6 +151,10 @@
 	status = "okay";
 };
 
+&ohci {
+	status = "okay";
+};
+
 &spi0 {
 	status = "okay";
 	label = "LS-SPI0";
@@ -161,3 +169,8 @@
 	label = "LS-UART0";
 };
 /* No optional LS-UART1 on Low Speed Expansion Connector. */
+
+&usb2_phy1 {
+	status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 75865f8a..422aeaf 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -106,6 +106,11 @@
 			#reset-cells = <2>;
 		};
 
+		peri_ctrl: system-controller at 8a20000 {
+			compatible = "syscon";
+			reg = <0x8a20000 0x1000>;
+		};
+
 		uart0: serial at 8b00000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x8b00000 0x1000>;
@@ -407,5 +412,47 @@
 			clocks = <&sysctrl HISTB_IR_CLK>;
 			status = "disabled";
 		};
+
+		ehci: ehci at 0x9890000 {
+			compatible = "generic-ehci";
+			reg = <0x9890000 0x10000>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_USB2_BUS_CLK>,
+				 <&crg HISTB_USB2_PHY_CLK>;
+			clock-names = "ehci_system", "phy";
+			resets = <&crg 0xb8 12>,
+				 <&crg 0xb8 16>;
+			reset-names = "bus", "phy";
+			status = "disabled";
+		};
+
+		ohci: ohci at 0x9880000 {
+			compatible = "generic-ohci";
+			reg = <0x9880000 0x10000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg HISTB_USB2_BUS_CLK>,
+				 <&crg HISTB_USB2_12M_CLK>,
+				 <&crg HISTB_USB2_48M_CLK>;
+			clock-names = "ahb_biu", "clk12", "clk48";
+			resets = <&crg 0xb8 12>;
+			reset-names = "bus";
+			status = "disabled";
+		};
+
+		usb2_phy1: usb-phy at 1 {
+			compatible = "hisilicon,hi3798cv200-usb2-phy";
+			#phy-cells = <0>;
+			hisilicon,peripheral-syscon = <&peri_ctrl>;
+			clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+			resets = <&crg 0xbc 4>;
+			reset-names = "por_rst";
+			status = "disabled";
+
+			usb2_port1: port at 1 {
+				clocks = <&crg HISTB_USB2_UTMI_CLK>;
+				resets = <&crg 0xbc 9>, <&crg 0xb8 13>;
+				reset-names = "port_rst", "utmi_rst";
+			};
+		};
 	};
 };
-- 
1.9.1

[PATCH 5/5] arm64: defconfig: enable some drivers and configs for hi3798cv200-poplar board.

[Jiancheng Xue]

Enable GMAC,I2C,IR,USB2-PHY for hi3798cv200-poplar board.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
---
 arch/arm64/configs/defconfig | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 97c123e..b45d760 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -31,6 +31,8 @@ CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_BCM2835=y
@@ -179,6 +181,7 @@ CONFIG_VIRTIO_NET=y
 CONFIG_AMD_XGBE=y
 CONFIG_NET_XGENE=y
 CONFIG_MACB=y
+CONFIG_HIX5HD2_GMAC=y
 CONFIG_HNS_DSAF=y
 CONFIG_HNS_ENET=y
 CONFIG_E1000E=y
@@ -259,6 +262,7 @@ CONFIG_I2C_TEGRA=y
 CONFIG_I2C_UNIPHIER_F=y
 CONFIG_I2C_RCAR=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_HIX5HD2=y
 CONFIG_SPI=y
 CONFIG_SPI_BCM2835=m
 CONFIG_SPI_BCM2835AUX=m
@@ -277,6 +281,7 @@ CONFIG_PINCTRL_MSM8994=y
 CONFIG_PINCTRL_MSM8996=y
 CONFIG_PINCTRL_QDF2XXX=y
 CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_PL061=y
 CONFIG_GPIO_RCAR=y
@@ -322,7 +327,7 @@ CONFIG_REGULATOR_QCOM_SMD_RPM=y
 CONFIG_REGULATOR_QCOM_SPMI=y
 CONFIG_REGULATOR_RK808=y
 CONFIG_REGULATOR_S2MPS11=y
-CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
 CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
@@ -359,6 +364,10 @@ CONFIG_BACKLIGHT_GENERIC=m
 CONFIG_BACKLIGHT_LP855X=m
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
+CONFIG_MEDIA_RC_SUPPORT=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_HIX5HD2=y
+CONFIG_LIRC=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_SOUND=y
@@ -488,7 +497,9 @@ CONFIG_PWM_MESON=m
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_PWM_SAMSUNG=y
 CONFIG_PWM_TEGRA=m
+CONFIG_TI_SYSCON_RESET=y
 CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_HISI_INNO_USB2=y
 CONFIG_PHY_HI6220_USB=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-- 
1.9.1

[PATCH 5/5] arm64: defconfig: enable some drivers and configs for hi3798cv200-poplar board.

[Jiancheng Xue]

Enable GMAC,I2C,IR,USB2-PHY for hi3798cv200-poplar board.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
---
 arch/arm64/configs/defconfig | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 97c123e..b45d760 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -31,6 +31,8 @@ CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_BCM2835=y
@@ -179,6 +181,7 @@ CONFIG_VIRTIO_NET=y
 CONFIG_AMD_XGBE=y
 CONFIG_NET_XGENE=y
 CONFIG_MACB=y
+CONFIG_HIX5HD2_GMAC=y
 CONFIG_HNS_DSAF=y
 CONFIG_HNS_ENET=y
 CONFIG_E1000E=y
@@ -259,6 +262,7 @@ CONFIG_I2C_TEGRA=y
 CONFIG_I2C_UNIPHIER_F=y
 CONFIG_I2C_RCAR=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_HIX5HD2=y
 CONFIG_SPI=y
 CONFIG_SPI_BCM2835=m
 CONFIG_SPI_BCM2835AUX=m
@@ -277,6 +281,7 @@ CONFIG_PINCTRL_MSM8994=y
 CONFIG_PINCTRL_MSM8996=y
 CONFIG_PINCTRL_QDF2XXX=y
 CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_PL061=y
 CONFIG_GPIO_RCAR=y
@@ -322,7 +327,7 @@ CONFIG_REGULATOR_QCOM_SMD_RPM=y
 CONFIG_REGULATOR_QCOM_SPMI=y
 CONFIG_REGULATOR_RK808=y
 CONFIG_REGULATOR_S2MPS11=y
-CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
 CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
@@ -359,6 +364,10 @@ CONFIG_BACKLIGHT_GENERIC=m
 CONFIG_BACKLIGHT_LP855X=m
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
+CONFIG_MEDIA_RC_SUPPORT=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_HIX5HD2=y
+CONFIG_LIRC=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_SOUND=y
@@ -488,7 +497,9 @@ CONFIG_PWM_MESON=m
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_PWM_SAMSUNG=y
 CONFIG_PWM_TEGRA=m
+CONFIG_TI_SYSCON_RESET=y
 CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_HISI_INNO_USB2=y
 CONFIG_PHY_HI6220_USB=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-- 
1.9.1

[PATCH 5/5] arm64: defconfig: enable some drivers and configs for hi3798cv200-poplar board.

[Jiancheng Xue]

Enable GMAC,I2C,IR,USB2-PHY for hi3798cv200-poplar board.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
---
 arch/arm64/configs/defconfig | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 97c123e..b45d760 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -31,6 +31,8 @@ CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_BCM2835=y
@@ -179,6 +181,7 @@ CONFIG_VIRTIO_NET=y
 CONFIG_AMD_XGBE=y
 CONFIG_NET_XGENE=y
 CONFIG_MACB=y
+CONFIG_HIX5HD2_GMAC=y
 CONFIG_HNS_DSAF=y
 CONFIG_HNS_ENET=y
 CONFIG_E1000E=y
@@ -259,6 +262,7 @@ CONFIG_I2C_TEGRA=y
 CONFIG_I2C_UNIPHIER_F=y
 CONFIG_I2C_RCAR=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_HIX5HD2=y
 CONFIG_SPI=y
 CONFIG_SPI_BCM2835=m
 CONFIG_SPI_BCM2835AUX=m
@@ -277,6 +281,7 @@ CONFIG_PINCTRL_MSM8994=y
 CONFIG_PINCTRL_MSM8996=y
 CONFIG_PINCTRL_QDF2XXX=y
 CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_PL061=y
 CONFIG_GPIO_RCAR=y
@@ -322,7 +327,7 @@ CONFIG_REGULATOR_QCOM_SMD_RPM=y
 CONFIG_REGULATOR_QCOM_SPMI=y
 CONFIG_REGULATOR_RK808=y
 CONFIG_REGULATOR_S2MPS11=y
-CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
 CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
@@ -359,6 +364,10 @@ CONFIG_BACKLIGHT_GENERIC=m
 CONFIG_BACKLIGHT_LP855X=m
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
+CONFIG_MEDIA_RC_SUPPORT=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_HIX5HD2=y
+CONFIG_LIRC=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_SOUND=y
@@ -488,7 +497,9 @@ CONFIG_PWM_MESON=m
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_PWM_SAMSUNG=y
 CONFIG_PWM_TEGRA=m
+CONFIG_TI_SYSCON_RESET=y
 CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_HISI_INNO_USB2=y
 CONFIG_PHY_HI6220_USB=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-- 
1.9.1

Re: [project-aspen-dev] [PATCH 3/5] phy: add inno-usb2-phy driver for hi3798cv200 SoC

[Daniel Thompson]

On 21/06/17 10:00, Jiancheng Xue wrote:
> From: Pengcheng Li <lpc.li@hisilicon.com>
> 
> Add inno-usb2-phy driver for hi3798cv200 SoC.
> 
> Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> ---
>   drivers/phy/Kconfig              |  10 ++
>   drivers/phy/Makefile             |   1 +
>   drivers/phy/phy-hisi-inno-usb2.c | 287 +++++++++++++++++++++++++++++++++++++++
>   3 files changed, 298 insertions(+)
>   create mode 100644 drivers/phy/phy-hisi-inno-usb2.c
> 
> ...
> diff --git a/drivers/phy/phy-hisi-inno-usb2.c b/drivers/phy/phy-hisi-inno-usb2.c
> new file mode 100644
> index 0000000..582c500
> --- /dev/null
> +++ b/drivers/phy/phy-hisi-inno-usb2.c
> @@ -0,0 +1,287 @@
 > ...> +static int hisi_inno_phy_of_get_ports(struct device *dev,
> +					struct  hisi_inno_phy_priv *priv)
> +{
> +	struct device_node *node = dev->of_node;
> +	struct device_node *child;
> +	int port = 0;
> +	int ret;
> +
> +	priv->port_num = of_get_child_count(node);
> +	if (priv->port_num > MAX_PORTS) {
> +		dev_err(dev, "too many ports : %d (max = %d)\n",
> +				priv->port_num, MAX_PORTS);
> +		return -EINVAL;
> +	}
> +
> +	priv->ports = devm_kcalloc(dev, priv->port_num,
> +				sizeof(struct hisi_inno_phy_port), GFP_KERNEL);
> +	if (!priv->ports)
> +		return -ENOMEM;
> +
> +	for_each_child_of_node(node, child) {
> +		struct hisi_inno_phy_port *phy_port = &priv->ports[port];
> +
> +		phy_port->utmi_clk = devm_get_clk_from_child(dev, child, NULL);
> +		if (IS_ERR(phy_port->utmi_clk)) {
> +			ret = PTR_ERR(phy_port->utmi_clk);
> +			goto fail;
> +		}
> +
> +		phy_port->port_rst = of_reset_control_get_exclusive(child, "port_rst"); > +		if (IS_ERR(phy_port->port_rst)) {
> +			ret = PTR_ERR(phy_port->port_rst);
> +			goto fail;
> +		}
> +
> +		phy_port->utmi_rst = of_reset_control_get_exclusive(child, "utmi_rst");
> +		if (IS_ERR(phy_port->utmi_rst)) {
> +			ret = PTR_ERR(phy_port->utmi_rst);
> +			reset_control_put(phy_port->port_rst);
> +			goto fail;
> +		}
> +		port++;
> +	}
> +
> +	return 0;
> +
> +fail:
> +	while (--port >= 0) {
> +		struct hisi_inno_phy_port *phy_port = &priv->ports[port];
> +
> +		reset_control_put(phy_port->utmi_rst);
> +		reset_control_put(phy_port->port_rst) > +		clk_put(phy_port->utmi_clk);

clk_put() should not be needed here.

> +	}

Do we also need clean up code like this in a remove callback?


Daniel.

[project-aspen-dev] [PATCH 3/5] phy: add inno-usb2-phy driver for hi3798cv200 SoC

[Daniel Thompson]

On 21/06/17 10:00, Jiancheng Xue wrote:
> From: Pengcheng Li <lpc.li@hisilicon.com>
> 
> Add inno-usb2-phy driver for hi3798cv200 SoC.
> 
> Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> ---
>   drivers/phy/Kconfig              |  10 ++
>   drivers/phy/Makefile             |   1 +
>   drivers/phy/phy-hisi-inno-usb2.c | 287 +++++++++++++++++++++++++++++++++++++++
>   3 files changed, 298 insertions(+)
>   create mode 100644 drivers/phy/phy-hisi-inno-usb2.c
> 
> ...
> diff --git a/drivers/phy/phy-hisi-inno-usb2.c b/drivers/phy/phy-hisi-inno-usb2.c
> new file mode 100644
> index 0000000..582c500
> --- /dev/null
> +++ b/drivers/phy/phy-hisi-inno-usb2.c
> @@ -0,0 +1,287 @@
 > ...> +static int hisi_inno_phy_of_get_ports(struct device *dev,
> +					struct  hisi_inno_phy_priv *priv)
> +{
> +	struct device_node *node = dev->of_node;
> +	struct device_node *child;
> +	int port = 0;
> +	int ret;
> +
> +	priv->port_num = of_get_child_count(node);
> +	if (priv->port_num > MAX_PORTS) {
> +		dev_err(dev, "too many ports : %d (max = %d)\n",
> +				priv->port_num, MAX_PORTS);
> +		return -EINVAL;
> +	}
> +
> +	priv->ports = devm_kcalloc(dev, priv->port_num,
> +				sizeof(struct hisi_inno_phy_port), GFP_KERNEL);
> +	if (!priv->ports)
> +		return -ENOMEM;
> +
> +	for_each_child_of_node(node, child) {
> +		struct hisi_inno_phy_port *phy_port = &priv->ports[port];
> +
> +		phy_port->utmi_clk = devm_get_clk_from_child(dev, child, NULL);
> +		if (IS_ERR(phy_port->utmi_clk)) {
> +			ret = PTR_ERR(phy_port->utmi_clk);
> +			goto fail;
> +		}
> +
> +		phy_port->port_rst = of_reset_control_get_exclusive(child, "port_rst"); > +		if (IS_ERR(phy_port->port_rst)) {
> +			ret = PTR_ERR(phy_port->port_rst);
> +			goto fail;
> +		}
> +
> +		phy_port->utmi_rst = of_reset_control_get_exclusive(child, "utmi_rst");
> +		if (IS_ERR(phy_port->utmi_rst)) {
> +			ret = PTR_ERR(phy_port->utmi_rst);
> +			reset_control_put(phy_port->port_rst);
> +			goto fail;
> +		}
> +		port++;
> +	}
> +
> +	return 0;
> +
> +fail:
> +	while (--port >= 0) {
> +		struct hisi_inno_phy_port *phy_port = &priv->ports[port];
> +
> +		reset_control_put(phy_port->utmi_rst);
> +		reset_control_put(phy_port->port_rst) > +		clk_put(phy_port->utmi_clk);

clk_put() should not be needed here.

> +	}

Do we also need clean up code like this in a remove callback?


Daniel.

Re: [PATCH 1/5] clk: hisilicon: add usb2 clocks for hi3798cv200 SoC

[Stephen Boyd]

On 06/21, Jiancheng Xue wrote:
> Add usb2 clocks for hi3798cv200 SoC.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/5] clk: hisilicon: add usb2 clocks for hi3798cv200 SoC

[Stephen Boyd]

On 06/21, Jiancheng Xue wrote:
> Add usb2 clocks for hi3798cv200 SoC.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/5] dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy

[Jiancheng Xue]

Hi,

On 2017/6/21 17:00, Jiancheng Xue wrote:
> Add support for hisi-inno-usb2 phy.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> ---
>  .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 36 ++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> new file mode 100644
> index 0000000..21f8208
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> @@ -0,0 +1,36 @@
> +HiSilicon INNO USB2 PHY
> +-----------------------
> +Required properties:
> +- compatible: Should be one of the following strings:
> +		"hisilicon,inno-usb2-phy",
> +		"hisilicon,hi3798cv200-usb2-phy",
> +- #phy-cells: Must be 0
> +- hisilicon,peripheral-syscon: Phandle of syscon used to control phy.

Here a property should be added to supply offsets of phy specific registers
in the above peripheral syscon.  I will modify this in the next version.

---
Regards,
Jiancheng

> +- clocks: Phandle and clock specifier pair for reference clock utmi_refclk.
> +- resets: List of phandle and reset specifier pairs for each reset signal in
> +reset-names.
> +- reset-names: Should be "por_rst" and "test_rst". The test_rst only
> +exists in some of SOCs, so it is optional.
> +
> +Phy node can include up to four subnodes. Each subnode represents one port.
> +The required properties of port node are as follows:
> +- clocks: Phandle and clock specifier pair for utmi_clock.
> +- resets: List of phandle and reset specifier pairs for port reset and utmi reset.
> +- reset-names: List of reset signal names. Should be "port_rst" and "utmi_rst"
> +
> +Refer to phy/phy-bindings.txt for the generic PHY binding properties
> +
> +Example:
> +usb_phy: phy {
> +		 compatible = "hisilicon,inno_usb2_phy";
> +		 #phy-cells = <0>;
> +		 hisilicon,peripheral-syscon = <&peri_ctrl>;
> +		 clocks = <&crg USB2_REF_CLK>;
> +		 resets = <&crg 0xb4 2>;
> +		 reset-names = "por_rst";
> +		 port0 {
> +			 clocks = <&crg USB2_UTMI0_CLK>;
> +			 resets = <&crg 0xb4 5>, <&crg 0xb4 1>;
> +			 reset-names = "port_rst", "utmi_rst";
> +		 };
> +	 };
> 

Re: [PATCH 2/5] dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy

[Jiancheng Xue]

Hi,

On 2017/6/21 17:00, Jiancheng Xue wrote:
> Add support for hisi-inno-usb2 phy.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> ---
>  .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 36 ++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> new file mode 100644
> index 0000000..21f8208
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> @@ -0,0 +1,36 @@
> +HiSilicon INNO USB2 PHY
> +-----------------------
> +Required properties:
> +- compatible: Should be one of the following strings:
> +		"hisilicon,inno-usb2-phy",
> +		"hisilicon,hi3798cv200-usb2-phy",
> +- #phy-cells: Must be 0
> +- hisilicon,peripheral-syscon: Phandle of syscon used to control phy.

Here a property should be added to supply offsets of phy specific registers
in the above peripheral syscon.  I will modify this in the next version.

---
Regards,
Jiancheng

> +- clocks: Phandle and clock specifier pair for reference clock utmi_refclk.
> +- resets: List of phandle and reset specifier pairs for each reset signal in
> +reset-names.
> +- reset-names: Should be "por_rst" and "test_rst". The test_rst only
> +exists in some of SOCs, so it is optional.
> +
> +Phy node can include up to four subnodes. Each subnode represents one port.
> +The required properties of port node are as follows:
> +- clocks: Phandle and clock specifier pair for utmi_clock.
> +- resets: List of phandle and reset specifier pairs for port reset and utmi reset.
> +- reset-names: List of reset signal names. Should be "port_rst" and "utmi_rst"
> +
> +Refer to phy/phy-bindings.txt for the generic PHY binding properties
> +
> +Example:
> +usb_phy: phy {
> +		 compatible = "hisilicon,inno_usb2_phy";
> +		 #phy-cells = <0>;
> +		 hisilicon,peripheral-syscon = <&peri_ctrl>;
> +		 clocks = <&crg USB2_REF_CLK>;
> +		 resets = <&crg 0xb4 2>;
> +		 reset-names = "por_rst";
> +		 port0 {
> +			 clocks = <&crg USB2_UTMI0_CLK>;
> +			 resets = <&crg 0xb4 5>, <&crg 0xb4 1>;
> +			 reset-names = "port_rst", "utmi_rst";
> +		 };
> +	 };
> 

Re: [PATCH 2/5] dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy

[Rob Herring]

On Wed, Jun 21, 2017 at 05:00:42PM +0800, Jiancheng Xue wrote:
> Add support for hisi-inno-usb2 phy.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> ---
>  .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 36 ++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> new file mode 100644
> index 0000000..21f8208
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> @@ -0,0 +1,36 @@
> +HiSilicon INNO USB2 PHY
> +-----------------------
> +Required properties:
> +- compatible: Should be one of the following strings:
> +		"hisilicon,inno-usb2-phy",
> +		"hisilicon,hi3798cv200-usb2-phy",
> +- #phy-cells: Must be 0
> +- hisilicon,peripheral-syscon: Phandle of syscon used to control phy.
> +- clocks: Phandle and clock specifier pair for reference clock utmi_refclk.
> +- resets: List of phandle and reset specifier pairs for each reset signal in
> +reset-names.
> +- reset-names: Should be "por_rst" and "test_rst". The test_rst only
> +exists in some of SOCs, so it is optional.

_rst is redundant.

> +
> +Phy node can include up to four subnodes. Each subnode represents one port.
> +The required properties of port node are as follows:
> +- clocks: Phandle and clock specifier pair for utmi_clock.
> +- resets: List of phandle and reset specifier pairs for port reset and utmi reset.
> +- reset-names: List of reset signal names. Should be "port_rst" and "utmi_rst"
> +
> +Refer to phy/phy-bindings.txt for the generic PHY binding properties
> +
> +Example:
> +usb_phy: phy {
> +		 compatible = "hisilicon,inno_usb2_phy";

Doesn't match the above compatible.

> +		 #phy-cells = <0>;
> +		 hisilicon,peripheral-syscon = <&peri_ctrl>;
> +		 clocks = <&crg USB2_REF_CLK>;
> +		 resets = <&crg 0xb4 2>;
> +		 reset-names = "por_rst";
> +		 port0 {

port@0 and provide a reg property.

> +			 clocks = <&crg USB2_UTMI0_CLK>;
> +			 resets = <&crg 0xb4 5>, <&crg 0xb4 1>;
> +			 reset-names = "port_rst", "utmi_rst";
> +		 };
> +	 };
> -- 
> 1.9.1
> 
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[PATCH 2/5] dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy

[Rob Herring]

On Wed, Jun 21, 2017 at 05:00:42PM +0800, Jiancheng Xue wrote:
> Add support for hisi-inno-usb2 phy.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> ---
>  .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 36 ++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> new file mode 100644
> index 0000000..21f8208
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> @@ -0,0 +1,36 @@
> +HiSilicon INNO USB2 PHY
> +-----------------------
> +Required properties:
> +- compatible: Should be one of the following strings:
> +		"hisilicon,inno-usb2-phy",
> +		"hisilicon,hi3798cv200-usb2-phy",
> +- #phy-cells: Must be 0
> +- hisilicon,peripheral-syscon: Phandle of syscon used to control phy.
> +- clocks: Phandle and clock specifier pair for reference clock utmi_refclk.
> +- resets: List of phandle and reset specifier pairs for each reset signal in
> +reset-names.
> +- reset-names: Should be "por_rst" and "test_rst". The test_rst only
> +exists in some of SOCs, so it is optional.

_rst is redundant.

> +
> +Phy node can include up to four subnodes. Each subnode represents one port.
> +The required properties of port node are as follows:
> +- clocks: Phandle and clock specifier pair for utmi_clock.
> +- resets: List of phandle and reset specifier pairs for port reset and utmi reset.
> +- reset-names: List of reset signal names. Should be "port_rst" and "utmi_rst"
> +
> +Refer to phy/phy-bindings.txt for the generic PHY binding properties
> +
> +Example:
> +usb_phy: phy {
> +		 compatible = "hisilicon,inno_usb2_phy";

Doesn't match the above compatible.

> +		 #phy-cells = <0>;
> +		 hisilicon,peripheral-syscon = <&peri_ctrl>;
> +		 clocks = <&crg USB2_REF_CLK>;
> +		 resets = <&crg 0xb4 2>;
> +		 reset-names = "por_rst";
> +		 port0 {

port at 0 and provide a reg property.

> +			 clocks = <&crg USB2_UTMI0_CLK>;
> +			 resets = <&crg 0xb4 5>, <&crg 0xb4 1>;
> +			 reset-names = "port_rst", "utmi_rst";
> +		 };
> +	 };
> -- 
> 1.9.1
> 
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