From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQD6C-0000ks-KV for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:33:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQD67-0004Nl-Ng for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:33:40 -0400 From: =?utf-8?b?TGx1w61z?= Vilanova Date: Wed, 28 Jun 2017 16:33:22 +0300 Message-Id: <149865680190.17063.16072451312204148936.stgit@frigg.lan> In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v11 19/29] target/arm: [tcg] Port to insn_start List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Emilio G. Cota" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Peter Crosthwaite , Paolo Bonzini , Peter Maydell , "open list:ARM" Incrementally paves the way towards using the generic instruction transla= tion loop. Signed-off-by: Llu=C3=ADs Vilanova --- target/arm/translate.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 029c4d3550..c7e188b50e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11898,6 +11898,26 @@ static void arm_trblock_tb_start(DisasContextBas= e *dcbase, CPUState *cpu) } } =20 +static void arm_trblock_insn_start(DisasContextBase *dcbase, CPUState *c= pu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> = 1), + 0); + +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >=3D 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp =3D DISAS_EXC; + } +#endif +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -11943,21 +11963,11 @@ void gen_intermediate_code(CPUState *cpu, Trans= lationBlock *tb) =20 do { dc->base.num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask= >> 1), - 0); + arm_trblock_insn_start(&dc->base, cpu); =20 -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >=3D 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->base.is_jmp =3D DISAS_EXC; + if (unlikely(dc->base.is_jmp > DISAS_NEXT)) { break; } -#endif =20 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { CPUBreakpoint *bp;