From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yogesh Gaur Date: Thu, 29 Jun 2017 16:00:35 +0530 Subject: [U-Boot] [PATCH] drivers:spi:sf: Add entry for micron, MT35XU512ABA1G12, flash Message-ID: <1498732235-18410-1-git-send-email-yogeshnarayan.gaur@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add entry for MT35XU512ABA1G12 flash in spi_flash_ids[] table. This flash supports subsector erase with 4KB granularity, have support of FSR(flag status register) and flash size is 64MB. Support of this flash is required for the upcoming NXP FlexSPI controller. Signed-off-by: Yogesh Gaur --- drivers/mtd/spi/spi_flash_ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index edca94e..f144cc3 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -133,6 +133,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"mt35xu512g", INFO6(0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR | SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ {"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, -- 1.9.1