From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 292A6C433E9 for ; Wed, 10 Mar 2021 14:43:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F06D964EDD for ; Wed, 10 Mar 2021 14:43:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232921AbhCJOnE (ORCPT ); Wed, 10 Mar 2021 09:43:04 -0500 Received: from out28-147.mail.aliyun.com ([115.124.28.147]:51366 "EHLO out28-147.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232975AbhCJOmr (ORCPT ); Wed, 10 Mar 2021 09:42:47 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436317|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.193297-0.00363244-0.80307;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047198;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=9;RT=9;SR=0;TI=SMTPD_---.Jj1IsSD_1615387362; Received: from 192.168.10.152(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.Jj1IsSD_1615387362) by smtp.aliyun-inc.com(10.147.42.22); Wed, 10 Mar 2021 22:42:43 +0800 Subject: Re: [PATCH 5/6] clk: ingenic: Support overriding PLLs M/N/OD calc algorithm To: Paul Cercueil , Michael Turquette , Stephen Boyd , Rob Herring Cc: od@zcrc.me, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org References: <20210307141759.30426-1-paul@crapouillou.net> <20210307141759.30426-6-paul@crapouillou.net> From: Zhou Yanjie Message-ID: <14fe0eed-5657-c555-f8eb-6e6b8b367b44@wanyeetech.com> Date: Wed, 10 Mar 2021 22:42:42 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20210307141759.30426-6-paul@crapouillou.net> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Paul, On 2021/3/7 下午10:17, Paul Cercueil wrote: > SoC-specific code can now provide a callback if they need to compute the > M/N/OD values in a specific way. > > Signed-off-by: Paul Cercueil > --- > drivers/clk/ingenic/cgu.c | 40 ++++++++++++++++++++++++++------------- > drivers/clk/ingenic/cgu.h | 3 +++ > 2 files changed, 30 insertions(+), 13 deletions(-) Tested-by: 周琰杰 (Zhou Yanjie) # on CU1000-neo/X1000E > diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c > index 58f7ab5cf0fe..266c7595d330 100644 > --- a/drivers/clk/ingenic/cgu.c > +++ b/drivers/clk/ingenic/cgu.c > @@ -119,28 +119,42 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) > n * od); > } > > -static unsigned long > -ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, > - unsigned long rate, unsigned long parent_rate, > - unsigned *pm, unsigned *pn, unsigned *pod) > +static void > +ingenic_pll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, > + unsigned long rate, unsigned long parent_rate, > + unsigned int *pm, unsigned int *pn, unsigned int *pod) > { > - const struct ingenic_cgu_pll_info *pll_info; > - unsigned m, n, od; > - > - pll_info = &clk_info->pll; > - od = 1; > + unsigned int m, n, od = 1; > > /* > * The frequency after the input divider must be between 10 and 50 MHz. > * The highest divider yields the best resolution. > */ > n = parent_rate / (10 * MHZ); > - n = min_t(unsigned, n, 1 << clk_info->pll.n_bits); > - n = max_t(unsigned, n, pll_info->n_offset); > + n = min_t(unsigned int, n, 1 << pll_info->n_bits); > + n = max_t(unsigned int, n, pll_info->n_offset); > > m = (rate / MHZ) * od * n / (parent_rate / MHZ); > - m = min_t(unsigned, m, 1 << clk_info->pll.m_bits); > - m = max_t(unsigned, m, pll_info->m_offset); > + m = min_t(unsigned int, m, 1 << pll_info->m_bits); > + m = max_t(unsigned int, m, pll_info->m_offset); > + > + *pm = m; > + *pn = n; > + *pod = od; > +} > + > +static unsigned long > +ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, > + unsigned long rate, unsigned long parent_rate, > + unsigned int *pm, unsigned int *pn, unsigned int *pod) > +{ > + const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; > + unsigned int m, n, od; > + > + if (pll_info->calc_m_n_od) > + (*pll_info->calc_m_n_od)(pll_info, rate, parent_rate, &m, &n, &od); > + else > + ingenic_pll_calc_m_n_od(pll_info, rate, parent_rate, &m, &n, &od); > > if (pm) > *pm = m; > diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h > index 10521d1b7b12..bfc2b9c38a41 100644 > --- a/drivers/clk/ingenic/cgu.h > +++ b/drivers/clk/ingenic/cgu.h > @@ -55,6 +55,9 @@ struct ingenic_cgu_pll_info { > s8 bypass_bit; > u8 enable_bit; > u8 stable_bit; > + void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, > + unsigned long rate, unsigned long parent_rate, > + unsigned int *m, unsigned int *n, unsigned int *od); > }; > > /**