From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lucky1.263xmail.com ([211.157.147.133]:48199 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753094AbdGSJ62 (ORCPT ); Wed, 19 Jul 2017 05:58:28 -0400 From: Shawn Lin To: Kishon Vijay Abraham I , Bjorn Helgaas Cc: Rob Herring , Heiko Stuebner , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Norris , Jeffy Chen , Shawn Lin Subject: [PATCH v5 7/7] dt-bindings: phy: convert to use per-lane Rockchip PCIe PHY Date: Wed, 19 Jul 2017 17:57:58 +0800 Message-Id: <1500458278-203082-3-git-send-email-shawn.lin@rock-chips.com> In-Reply-To: <1500458278-203082-1-git-send-email-shawn.lin@rock-chips.com> References: <1500458118-139042-1-git-send-email-shawn.lin@rock-chips.com> <1500458278-203082-1-git-send-email-shawn.lin@rock-chips.com> Sender: linux-pci-owner@vger.kernel.org List-ID: This patch deprecate the legacy PCIe PHY and encourage user to use per-lane PHY mode by setting #phy-cells to 1. Signed-off-by: Shawn Lin Acked-by: Rob Herring Reviewed-by: Brian Norris --- Changes in v5: None Changes in v4: None Changes in v3: - rename the commit tile Changes in v2: None Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt index 0f6222a..b496042 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt @@ -3,7 +3,6 @@ Rockchip PCIE PHY Required properties: - compatible: rockchip,rk3399-pcie-phy - - #phy-cells: must be 0 - clocks: Must contain an entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must be "refclk" @@ -11,6 +10,12 @@ Required properties: See ../reset/reset.txt for details. - reset-names: Must be "phy" +Required properties for legacy PHY mode (deprecated): + - #phy-cells: must be 0 + +Required properties for per-lane PHY mode (preferred): + - #phy-cells: must be 1 + Example: grf: syscon@ff770000 { -- 1.9.1