[U-Boot] [PATCH 5/6] x86: tsc: Correct Silvermont reference clock values

[Bin Meng <bmeng.cn@gmail.com>]

Atom processors use a 19.2 MHz crystal oscillator.

Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.

Later processors generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.

Update the Silvermont-based tables accordingly, matching the Software
Developers Manual.

Also, correct a 166 MHz entry that should have been 116 MHz, and add
a missing 80 MHz entry for VLV2.

This keeps in sync with Linux kernel commit:
  05680e7: x86/tsc_msr: Correct Silvermont reference clock values

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 drivers/timer/tsc_timer.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 3c1b745..b242e74 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -44,11 +44,11 @@ static struct freq_desc freq_desc_tables[] = {
 	/* CLV+ */
 	{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
 	/* TNG - Intel Atom processor Z3400 series */
-	{ 6, 0x4a, 1, { 0, 99840, 133200, 0, 0, 0, 0, 0 } },
+	{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
 	/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
-	{ 6, 0x37, 1, { 83200, 99840, 133200, 166400, 0, 0, 0, 0 } },
+	{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
 	/* ANN - Intel Atom processor Z3500 series */
-	{ 6, 0x5a, 1, { 83200, 99840, 133200, 99840, 0, 0, 0, 0 } },
+	{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
 	/* Ivybridge */
 	{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
 };
@@ -99,7 +99,7 @@ static unsigned long __maybe_unused try_msr_calibrate_tsc(void)
 
 	if (freq_desc_tables[cpu_index].msr_plat == 2) {
 		/* TODO: Figure out how best to deal with this */
-		freq = 99840;
+		freq = 100000;
 		debug("Using frequency: %u KHz\n", freq);
 	} else {
 		/* Get FSB FREQ ID */
-- 
2.9.2