* [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
@ 2017-06-12 1:47 ` Hoeun Ryu
0 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-06-12 1:47 UTC (permalink / raw)
To: Robin Murphy, Russell King; +Cc: Hoeun Ryu, linux-arm-kernel, linux-kernel
Reading TTBCR in early boot stage might return the value of the previous
kernel's configuration, especially in case of kexec. For example, if
normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
reserved area for crash kernel, reading TTBCR and using the value to OR
other bit fields might be risky because it doesn't have a reset value for
TTBCR.
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
---
* add Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
* v1: amended based on
- "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
PHYS_OFFSET > PAGE_OFFSET"
- https://lkml.org/lkml/2017/6/5/239
arch/arm/mm/proc-v7-3level.S | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 5e5720e..7d16bbc 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
.macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
- mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
- orr \tmp, \tmp, #TTB_EAE
+ mov \tmp, #TTB_EAE @ for TTB control egister
ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
@ 2017-06-12 1:47 ` Hoeun Ryu
0 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-06-12 1:47 UTC (permalink / raw)
To: linux-arm-kernel
Reading TTBCR in early boot stage might return the value of the previous
kernel's configuration, especially in case of kexec. For example, if
normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
reserved area for crash kernel, reading TTBCR and using the value to OR
other bit fields might be risky because it doesn't have a reset value for
TTBCR.
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
---
* add Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
* v1: amended based on
- "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
PHYS_OFFSET > PAGE_OFFSET"
- https://lkml.org/lkml/2017/6/5/239
arch/arm/mm/proc-v7-3level.S | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 5e5720e..7d16bbc 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
.macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
- mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
- orr \tmp, \tmp, #TTB_EAE
+ mov \tmp, #TTB_EAE @ for TTB control egister
ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
2017-06-12 1:47 ` Hoeun Ryu
@ 2017-07-03 8:18 ` Hoeun Ryu
-1 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-07-03 8:18 UTC (permalink / raw)
To: Robin Murphy, Russell King; +Cc: linux-arm-kernel, linux-kernel
Hello, Russell King.
Do you have a plan to include this patch in your tree ?
Thank you.
On Mon, 2017-06-12 at 10:47 +0900, Hoeun Ryu wrote:
> Reading TTBCR in early boot stage might return the value of the
> previous
> kernel's configuration, especially in case of kexec. For example, if
> normal kernel (first kernel) had run on a configuration of
> PHYS_OFFSET <=
> PAGE_OFFSET and crash kernel (second kernel) is running on a
> configuration
> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
> reserved area for crash kernel, reading TTBCR and using the value to
> OR
> other bit fields might be risky because it doesn't have a reset value
> for
> TTBCR.
>
> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> Suggested-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
>
> ---
>
> * add Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> * v1: amended based on
> - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
> PHYS_OFFSET > PAGE_OFFSET"
> - https://lkml.org/lkml/2017/6/5/239
>
> arch/arm/mm/proc-v7-3level.S | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-
> 3level.S
> index 5e5720e..7d16bbc 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
> .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
> ldr \tmp, =swapper_pg_dir @
> swapper_pg_dir virtual address
> cmp \ttbr1, \tmp, lsr #12 @
> PHYS_OFFSET > PAGE_OFFSET?
> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB
> control egister
> - orr \tmp, \tmp, #TTB_EAE
> + mov \tmp, #TTB_EAE @ for TTB
> control egister
> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
> ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
@ 2017-07-03 8:18 ` Hoeun Ryu
0 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-07-03 8:18 UTC (permalink / raw)
To: linux-arm-kernel
Hello, Russell King.
Do you have a plan to include this patch in your tree ?
Thank you.
On Mon, 2017-06-12 at 10:47 +0900, Hoeun Ryu wrote:
> ?Reading TTBCR in early boot stage might return the value of the
> previous
> kernel's configuration, especially in case of kexec. For example, if
> normal kernel (first kernel) had run on a configuration of
> PHYS_OFFSET <=
> PAGE_OFFSET and crash kernel (second kernel) is running on a
> configuration
> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
> reserved area for crash kernel, reading TTBCR and using the value to
> OR
> other bit fields might be risky because it doesn't have a reset value
> for
> TTBCR.
>
> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> Suggested-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
>
> ---
>
> ?* add Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> ?* v1: amended based on
> ?????- "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
> ????????PHYS_OFFSET > PAGE_OFFSET"
> ?????- https://lkml.org/lkml/2017/6/5/239
>
> ?arch/arm/mm/proc-v7-3level.S | 3 +--
> ?1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-
> 3level.S
> index 5e5720e..7d16bbc 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
> ? .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
> ? ldr \tmp, =swapper_pg_dir @
> swapper_pg_dir virtual address
> ? cmp \ttbr1, \tmp, lsr #12 @
> PHYS_OFFSET > PAGE_OFFSET?
> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB
> control egister
> - orr \tmp, \tmp, #TTB_EAE
> + mov \tmp, #TTB_EAE @ for TTB
> control egister
> ? ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
> ? ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
> ? ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
2017-06-12 1:47 ` Hoeun Ryu
@ 2017-08-04 6:07 ` Hoeun Ryu
-1 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-08-04 6:07 UTC (permalink / raw)
To: Robin Murphy, Russell King; +Cc: linux-arm-kernel, linux-kernel
Hello, Russell King.
The following patch has not merged yet.
Do you have a plan to accept and merge this patch ?
Thank you.
On Mon, 2017-06-12 at 10:47 +0900, Hoeun Ryu wrote:
> Reading TTBCR in early boot stage might return the value of the previous
> kernel's configuration, especially in case of kexec. For example, if
> normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
> PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
> reserved area for crash kernel, reading TTBCR and using the value to OR
> other bit fields might be risky because it doesn't have a reset value for
> TTBCR.
>
> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> Suggested-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
>
> ---
>
> * add Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> * v1: amended based on
> - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
> PHYS_OFFSET > PAGE_OFFSET"
> - https://lkml.org/lkml/2017/6/5/239
>
> arch/arm/mm/proc-v7-3level.S | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> index 5e5720e..7d16bbc 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
> .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
> ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
> cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
> - orr \tmp, \tmp, #TTB_EAE
> + mov \tmp, #TTB_EAE @ for TTB control egister
> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
> ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
@ 2017-08-04 6:07 ` Hoeun Ryu
0 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-08-04 6:07 UTC (permalink / raw)
To: linux-arm-kernel
Hello, Russell King.
The following patch has not merged yet.
Do you have a plan to accept and merge this patch ?
Thank you.
On Mon, 2017-06-12 at 10:47 +0900, Hoeun Ryu wrote:
> ?Reading TTBCR in early boot stage might return the value of the previous
> kernel's configuration, especially in case of kexec. For example, if
> normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
> PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
> reserved area for crash kernel, reading TTBCR and using the value to OR
> other bit fields might be risky because it doesn't have a reset value for
> TTBCR.
>
> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> Suggested-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
>
> ---
>
> ?* add Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
> ?* v1: amended based on
> ?????- "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
> ????????PHYS_OFFSET > PAGE_OFFSET"
> ?????- https://lkml.org/lkml/2017/6/5/239
>
> ?arch/arm/mm/proc-v7-3level.S | 3 +--
> ?1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> index 5e5720e..7d16bbc 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
> ? .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
> ? ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
> ? cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
> - orr \tmp, \tmp, #TTB_EAE
> + mov \tmp, #TTB_EAE @ for TTB control egister
> ? ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
> ? ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
> ? ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
2017-08-04 6:07 ` Hoeun Ryu
@ 2017-08-04 10:04 ` Robin Murphy
-1 siblings, 0 replies; 16+ messages in thread
From: Robin Murphy @ 2017-08-04 10:04 UTC (permalink / raw)
To: Hoeun Ryu; +Cc: Russell King, linux-arm-kernel, linux-kernel
On 04/08/17 07:07, Hoeun Ryu wrote:
> Hello, Russell King.
>
> The following patch has not merged yet.
> Do you have a plan to accept and merge this patch ?
This should probably go through the ARM tree, so please submit it to
Russell's patch-tracking system here:
http://www.armlinux.org.uk/developer/patches/
Robin.
>
> Thank you.
>
> On Mon, 2017-06-12 at 10:47 +0900, Hoeun Ryu wrote:
>> Reading TTBCR in early boot stage might return the value of the previous
>> kernel's configuration, especially in case of kexec. For example, if
>> normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
>> PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
>> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
>> reserved area for crash kernel, reading TTBCR and using the value to OR
>> other bit fields might be risky because it doesn't have a reset value for
>> TTBCR.
>>
>> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
>> Suggested-by: Robin Murphy <robin.murphy@arm.com>
>> Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
>>
>> ---
>>
>> * add Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
>> * v1: amended based on
>> - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
>> PHYS_OFFSET > PAGE_OFFSET"
>> - https://lkml.org/lkml/2017/6/5/239
>>
>> arch/arm/mm/proc-v7-3level.S | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
>> index 5e5720e..7d16bbc 100644
>> --- a/arch/arm/mm/proc-v7-3level.S
>> +++ b/arch/arm/mm/proc-v7-3level.S
>> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
>> .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
>> ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
>> cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
>> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
>> - orr \tmp, \tmp, #TTB_EAE
>> + mov \tmp, #TTB_EAE @ for TTB control egister
>> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
>> ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
>> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
@ 2017-08-04 10:04 ` Robin Murphy
0 siblings, 0 replies; 16+ messages in thread
From: Robin Murphy @ 2017-08-04 10:04 UTC (permalink / raw)
To: linux-arm-kernel
On 04/08/17 07:07, Hoeun Ryu wrote:
> Hello, Russell King.
>
> The following patch has not merged yet.
> Do you have a plan to accept and merge this patch ?
This should probably go through the ARM tree, so please submit it to
Russell's patch-tracking system here:
http://www.armlinux.org.uk/developer/patches/
Robin.
>
> Thank you.
>
> On Mon, 2017-06-12 at 10:47 +0900, Hoeun Ryu wrote:
>> Reading TTBCR in early boot stage might return the value of the previous
>> kernel's configuration, especially in case of kexec. For example, if
>> normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
>> PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
>> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
>> reserved area for crash kernel, reading TTBCR and using the value to OR
>> other bit fields might be risky because it doesn't have a reset value for
>> TTBCR.
>>
>> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
>> Suggested-by: Robin Murphy <robin.murphy@arm.com>
>> Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
>>
>> ---
>>
>> * add Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
>> * v1: amended based on
>> - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
>> PHYS_OFFSET > PAGE_OFFSET"
>> - https://lkml.org/lkml/2017/6/5/239
>>
>> arch/arm/mm/proc-v7-3level.S | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
>> index 5e5720e..7d16bbc 100644
>> --- a/arch/arm/mm/proc-v7-3level.S
>> +++ b/arch/arm/mm/proc-v7-3level.S
>> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
>> .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
>> ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
>> cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
>> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
>> - orr \tmp, \tmp, #TTB_EAE
>> + mov \tmp, #TTB_EAE @ for TTB control egister
>> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
>> ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
>> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
2017-08-04 10:04 ` Robin Murphy
@ 2017-08-04 13:26 ` Hoeun Ryu
-1 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-08-04 13:26 UTC (permalink / raw)
To: Robin Murphy; +Cc: Russell King, linux-arm-kernel, linux-kernel
2017. 8. 4. 오후 7:04 Robin Murphy <robin.murphy@arm.com> 작성:
>> On 04/08/17 07:07, Hoeun Ryu wrote:
>> Hello, Russell King.
>>
>> The following patch has not merged yet.
>> Do you have a plan to accept and merge this patch ?
>
> This should probably go through the ARM tree, so please submit it to
> Russell's patch-tracking system here:
>
> http://www.armlinux.org.uk/developer/patches/
Thank you for the reply, I'll try it.
>
> Robin.
>
>>
>> Thank you.
>>
>>> On Mon, 2017-06-12 at 10:47 +0900, Hoeun Ryu wrote:
>>> Reading TTBCR in early boot stage might return the value of the previous
>>> kernel's configuration, especially in case of kexec. For example, if
>>> normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
>>> PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
>>> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
>>> reserved area for crash kernel, reading TTBCR and using the value to OR
>>> other bit fields might be risky because it doesn't have a reset value for
>>> TTBCR.
>>>
>>> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
>>> Suggested-by: Robin Murphy <robin.murphy@arm.com>
>>> Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
>>>
>>> ---
>>>
>>> * add Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
>>> * v1: amended based on
>>> - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
>>> PHYS_OFFSET > PAGE_OFFSET"
>>> - https://lkml.org/lkml/2017/6/5/239
>>>
>>> arch/arm/mm/proc-v7-3level.S | 3 +--
>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
>>> index 5e5720e..7d16bbc 100644
>>> --- a/arch/arm/mm/proc-v7-3level.S
>>> +++ b/arch/arm/mm/proc-v7-3level.S
>>> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
>>> .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
>>> ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
>>> cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
>>> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
>>> - orr \tmp, \tmp, #TTB_EAE
>>> + mov \tmp, #TTB_EAE @ for TTB control egister
>>> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
>>> ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
>>> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
@ 2017-08-04 13:26 ` Hoeun Ryu
0 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-08-04 13:26 UTC (permalink / raw)
To: linux-arm-kernel
2017. 8. 4. ?? 7:04 Robin Murphy <robin.murphy@arm.com> ??:
>> On 04/08/17 07:07, Hoeun Ryu wrote:
>> Hello, Russell King.
>>
>> The following patch has not merged yet.
>> Do you have a plan to accept and merge this patch ?
>
> This should probably go through the ARM tree, so please submit it to
> Russell's patch-tracking system here:
>
> http://www.armlinux.org.uk/developer/patches/
Thank you for the reply, I'll try it.
>
> Robin.
>
>>
>> Thank you.
>>
>>> On Mon, 2017-06-12 at 10:47 +0900, Hoeun Ryu wrote:
>>> Reading TTBCR in early boot stage might return the value of the previous
>>> kernel's configuration, especially in case of kexec. For example, if
>>> normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
>>> PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
>>> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
>>> reserved area for crash kernel, reading TTBCR and using the value to OR
>>> other bit fields might be risky because it doesn't have a reset value for
>>> TTBCR.
>>>
>>> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
>>> Suggested-by: Robin Murphy <robin.murphy@arm.com>
>>> Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
>>>
>>> ---
>>>
>>> * add Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
>>> * v1: amended based on
>>> - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
>>> PHYS_OFFSET > PAGE_OFFSET"
>>> - https://lkml.org/lkml/2017/6/5/239
>>>
>>> arch/arm/mm/proc-v7-3level.S | 3 +--
>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
>>> index 5e5720e..7d16bbc 100644
>>> --- a/arch/arm/mm/proc-v7-3level.S
>>> +++ b/arch/arm/mm/proc-v7-3level.S
>>> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
>>> .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
>>> ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
>>> cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
>>> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
>>> - orr \tmp, \tmp, #TTB_EAE
>>> + mov \tmp, #TTB_EAE @ for TTB control egister
>>> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
>>> ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
>>> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
2017-06-10 4:43 ` Hoeun Ryu
@ 2017-06-10 10:19 ` Russell King - ARM Linux
-1 siblings, 0 replies; 16+ messages in thread
From: Russell King - ARM Linux @ 2017-06-10 10:19 UTC (permalink / raw)
To: Hoeun Ryu; +Cc: Robin Murphy, linux-kernel, linux-arm-kernel
On Sat, Jun 10, 2017 at 01:43:24PM +0900, Hoeun Ryu wrote:
> Hello, Russell and Robin.
>
> Would you please review this patch ?
I think it's fine, thanks.
>
> Than you
>
> > On Jun 7, 2017, at 11:39 AM, Hoeun Ryu <hoeun.ryu@gmail.com> wrote:
> >
> > Reading TTBCR in early boot stage might return the value of the previous
> > kernel's configuration, especially in case of kexec. For example, if
> > normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
> > PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
> > PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
> > reserved area for crash kernel, reading TTBCR and using the value to OR
> > other bit fields might be risky because it doesn't have a reset value for
> > TTBCR.
> >
> > Suggested-by: Robin Murphy <robin.murphy@arm.com>
> > Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
> > ---
> >
> > * v1: amended based on
> > - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
> > PHYS_OFFSET > PAGE_OFFSET"
> > - https://lkml.org/lkml/2017/6/5/239
> >
> > arch/arm/mm/proc-v7-3level.S | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> > index 5e5720e..7d16bbc 100644
> > --- a/arch/arm/mm/proc-v7-3level.S
> > +++ b/arch/arm/mm/proc-v7-3level.S
> > @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
> > .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
> > ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
> > cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
> > - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
> > - orr \tmp, \tmp, #TTB_EAE
> > + mov \tmp, #TTB_EAE @ for TTB control egister
> > ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
> > ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
> > ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
> > --
> > 2.7.4
> >
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
@ 2017-06-10 10:19 ` Russell King - ARM Linux
0 siblings, 0 replies; 16+ messages in thread
From: Russell King - ARM Linux @ 2017-06-10 10:19 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Jun 10, 2017 at 01:43:24PM +0900, Hoeun Ryu wrote:
> Hello, Russell and Robin.
>
> Would you please review this patch ?
I think it's fine, thanks.
>
> Than you
>
> > On Jun 7, 2017, at 11:39 AM, Hoeun Ryu <hoeun.ryu@gmail.com> wrote:
> >
> > Reading TTBCR in early boot stage might return the value of the previous
> > kernel's configuration, especially in case of kexec. For example, if
> > normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
> > PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
> > PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
> > reserved area for crash kernel, reading TTBCR and using the value to OR
> > other bit fields might be risky because it doesn't have a reset value for
> > TTBCR.
> >
> > Suggested-by: Robin Murphy <robin.murphy@arm.com>
> > Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
> > ---
> >
> > * v1: amended based on
> > - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
> > PHYS_OFFSET > PAGE_OFFSET"
> > - https://lkml.org/lkml/2017/6/5/239
> >
> > arch/arm/mm/proc-v7-3level.S | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> > index 5e5720e..7d16bbc 100644
> > --- a/arch/arm/mm/proc-v7-3level.S
> > +++ b/arch/arm/mm/proc-v7-3level.S
> > @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
> > .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
> > ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
> > cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
> > - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
> > - orr \tmp, \tmp, #TTB_EAE
> > + mov \tmp, #TTB_EAE @ for TTB control egister
> > ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
> > ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
> > ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
> > --
> > 2.7.4
> >
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
2017-06-07 2:39 ` Hoeun Ryu
@ 2017-06-10 4:43 ` Hoeun Ryu
-1 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-06-10 4:43 UTC (permalink / raw)
To: Robin Murphy, Russell King; +Cc: linux-arm-kernel, linux-kernel
Hello, Russell and Robin.
Would you please review this patch ?
Than you
> On Jun 7, 2017, at 11:39 AM, Hoeun Ryu <hoeun.ryu@gmail.com> wrote:
>
> Reading TTBCR in early boot stage might return the value of the previous
> kernel's configuration, especially in case of kexec. For example, if
> normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
> PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
> reserved area for crash kernel, reading TTBCR and using the value to OR
> other bit fields might be risky because it doesn't have a reset value for
> TTBCR.
>
> Suggested-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
> ---
>
> * v1: amended based on
> - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
> PHYS_OFFSET > PAGE_OFFSET"
> - https://lkml.org/lkml/2017/6/5/239
>
> arch/arm/mm/proc-v7-3level.S | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> index 5e5720e..7d16bbc 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
> .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
> ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
> cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
> - orr \tmp, \tmp, #TTB_EAE
> + mov \tmp, #TTB_EAE @ for TTB control egister
> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
> ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
@ 2017-06-10 4:43 ` Hoeun Ryu
0 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-06-10 4:43 UTC (permalink / raw)
To: linux-arm-kernel
Hello, Russell and Robin.
Would you please review this patch ?
Than you
> On Jun 7, 2017, at 11:39 AM, Hoeun Ryu <hoeun.ryu@gmail.com> wrote:
>
> Reading TTBCR in early boot stage might return the value of the previous
> kernel's configuration, especially in case of kexec. For example, if
> normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
> PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
> reserved area for crash kernel, reading TTBCR and using the value to OR
> other bit fields might be risky because it doesn't have a reset value for
> TTBCR.
>
> Suggested-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
> ---
>
> * v1: amended based on
> - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
> PHYS_OFFSET > PAGE_OFFSET"
> - https://lkml.org/lkml/2017/6/5/239
>
> arch/arm/mm/proc-v7-3level.S | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> index 5e5720e..7d16bbc 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
> .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
> ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
> cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
> - orr \tmp, \tmp, #TTB_EAE
> + mov \tmp, #TTB_EAE @ for TTB control egister
> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
> ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
@ 2017-06-07 2:39 ` Hoeun Ryu
0 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-06-07 2:39 UTC (permalink / raw)
To: Robin Murphy, Russell King; +Cc: Hoeun Ryu, linux-arm-kernel, linux-kernel
Reading TTBCR in early boot stage might return the value of the previous
kernel's configuration, especially in case of kexec. For example, if
normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
reserved area for crash kernel, reading TTBCR and using the value to OR
other bit fields might be risky because it doesn't have a reset value for
TTBCR.
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
---
* v1: amended based on
- "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
PHYS_OFFSET > PAGE_OFFSET"
- https://lkml.org/lkml/2017/6/5/239
arch/arm/mm/proc-v7-3level.S | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 5e5720e..7d16bbc 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
.macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
- mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
- orr \tmp, \tmp, #TTB_EAE
+ mov \tmp, #TTB_EAE @ for TTB control egister
ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup
@ 2017-06-07 2:39 ` Hoeun Ryu
0 siblings, 0 replies; 16+ messages in thread
From: Hoeun Ryu @ 2017-06-07 2:39 UTC (permalink / raw)
To: linux-arm-kernel
Reading TTBCR in early boot stage might return the value of the previous
kernel's configuration, especially in case of kexec. For example, if
normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <=
PAGE_OFFSET and crash kernel (second kernel) is running on a configuration
PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the
reserved area for crash kernel, reading TTBCR and using the value to OR
other bit fields might be risky because it doesn't have a reset value for
TTBCR.
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com>
---
* v1: amended based on
- "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when
PHYS_OFFSET > PAGE_OFFSET"
- https://lkml.org/lkml/2017/6/5/239
arch/arm/mm/proc-v7-3level.S | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 5e5720e..7d16bbc 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext)
.macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
- mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister
- orr \tmp, \tmp, #TTB_EAE
+ mov \tmp, #TTB_EAE @ for TTB control egister
ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2017-08-04 13:26 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-12 1:47 [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup Hoeun Ryu
2017-06-12 1:47 ` Hoeun Ryu
2017-07-03 8:18 ` Hoeun Ryu
2017-07-03 8:18 ` Hoeun Ryu
2017-08-04 6:07 ` Hoeun Ryu
2017-08-04 6:07 ` Hoeun Ryu
2017-08-04 10:04 ` Robin Murphy
2017-08-04 10:04 ` Robin Murphy
2017-08-04 13:26 ` Hoeun Ryu
2017-08-04 13:26 ` Hoeun Ryu
-- strict thread matches above, loose matches on Subject: below --
2017-06-07 2:39 Hoeun Ryu
2017-06-07 2:39 ` Hoeun Ryu
2017-06-10 4:43 ` Hoeun Ryu
2017-06-10 4:43 ` Hoeun Ryu
2017-06-10 10:19 ` Russell King - ARM Linux
2017-06-10 10:19 ` Russell King - ARM Linux
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