From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751724AbdHLN5Y (ORCPT ); Sat, 12 Aug 2017 09:57:24 -0400 Received: from mga11.intel.com ([192.55.52.93]:3828 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750948AbdHLN5W (ORCPT ); Sat, 12 Aug 2017 09:57:22 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,363,1498546800"; d="scan'208";a="1182051122" From: Yu Zhang To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, xiaoguangrong@tencent.com, joro@8bytes.org Subject: [PATCH v1 0/4] KVM: MMU: 5 level EPT/shadow support Date: Sat, 12 Aug 2017 21:35:02 +0800 Message-Id: <1502544906-1108-1-git-send-email-yu.c.zhang@linux.intel.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Intel's existing processors limit the maximum linear address width to 48 bits, and the maximum physical address width to 46 bits. And the upcoming processors will extend maximum linear address width to 57 bits and maximum physical address width can go upto 52 bits in practical. With linear address width greater than 48, a new paging mode in IA-32e is introduced - 5 level paging(also known as LA57). And to support VMs with this feature, KVM MMU code need to be extended. And to achieve this, this patchset: 1> leverages 2 qemu parameters: +la57 and phys-bits to expose wider linear address width and physical address width to the VM; 2> extends shadow logic to construct 5 level shadow page for VMs running in LA57 mode; 3> extends ept logic to construct 5 level ept table for VMs whose maximum physical width exceeds 48 bits. Yu Zhang (4): KVM: MMU: check guest CR3 reserved bits based on its physical address width. KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL. KVM: MMU: Add 5 level EPT & Shadow page table support. KVM: MMU: Expose the LA57 feature to VM. arch/x86/include/asm/kvm_host.h | 29 +++++---------------- arch/x86/include/asm/vmx.h | 1 + arch/x86/kvm/cpuid.c | 21 ++++++++++----- arch/x86/kvm/emulate.c | 24 +++++++++++------ arch/x86/kvm/kvm_cache_regs.h | 2 +- arch/x86/kvm/mmu.c | 58 +++++++++++++++++++++++++---------------- arch/x86/kvm/mmu.h | 8 +++++- arch/x86/kvm/mmu_audit.c | 4 +-- arch/x86/kvm/svm.c | 6 ++--- arch/x86/kvm/vmx.c | 27 ++++++++++++------- arch/x86/kvm/x86.c | 15 ++++++----- arch/x86/kvm/x86.h | 44 +++++++++++++++++++++++++++++++ 12 files changed, 158 insertions(+), 81 deletions(-) -- 2.5.0