From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58241) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhd5c-0006oW-GU for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:45:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dhd5X-00051o-Ho for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:45:04 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:60947) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhd5X-0004zJ-BT for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:44:59 -0400 From: Matt Redfearn Date: Tue, 15 Aug 2017 15:44:17 +0100 Message-ID: <1502808257-17395-1-git-send-email-matt.redfearn@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH] PCI: PCIe access should always be little endian List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S . Tsirkin" , Marcel Apfelbaum Cc: qemu-devel@nongnu.org, Yongbok Kim , Matt Redfearn PCIe busses are always little endian, so set the endianness of the memory region to little endian rather than native such that operations work as expected on big endian targets. Signed-off-by: Matt Redfearn --- hw/pci/pcie_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index dcebf57ed45e..553db56778b6 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -81,7 +81,7 @@ static uint64_t pcie_mmcfg_data_read(void *opaque, static const MemoryRegionOps pcie_mmcfg_ops = { .read = pcie_mmcfg_data_read, .write = pcie_mmcfg_data_write, - .endianness = DEVICE_NATIVE_ENDIAN, + .endianness = DEVICE_LITTLE_ENDIAN, }; static void pcie_host_init(Object *obj) -- 2.7.4