From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752074AbdH1DVj (ORCPT ); Sun, 27 Aug 2017 23:21:39 -0400 Received: from mail.cn.fujitsu.com ([183.91.158.132]:50429 "EHLO heian.cn.fujitsu.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752053AbdH1DVg (ORCPT ); Sun, 27 Aug 2017 23:21:36 -0400 X-IronPort-AV: E=Sophos;i="5.41,439,1498492800"; d="scan'208";a="24797617" From: Dou Liyang To: , , CC: , , , , , , , Dou Liyang Subject: [PATCH v8 08/13] x86/ioapic: Refactor the delay logic in timer_irq_works() Date: Mon, 28 Aug 2017 11:20:33 +0800 Message-ID: <1503890438-27840-9-git-send-email-douly.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1503890438-27840-1-git-send-email-douly.fnst@cn.fujitsu.com> References: <1503890438-27840-1-git-send-email-douly.fnst@cn.fujitsu.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.167.226.106] X-yoursite-MailScanner-ID: 7E0864724012.AFC94 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: douly.fnst@cn.fujitsu.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Kernel use timer_irq_works() to detects the timer IRQs. It calls mdelay(10) to delay ten ticks and check whether the timer IRQ work or not. The mdelay() depends on the loops_per_jiffy which is set up in calibrate_delay(). Current kernel defaults the IRQ 0 is available when it calibrates delay. But it is wrong in the dump-capture kernel with 'notsc' option inherited from 1st kernel option. dump-capture kernel can't make sure the timer IRQ works well. The correct design is making the interrupt mode setup and checking timer IRQ works in advance of calibrate_delay(). That results in the mdelay() being unusable in timer_irq_works(). Preparatory patch to make the setup in advance. Refactor the delay logic by waiting for some cycles. In the system with X86_FEATURE_TSC feature, Use rdtsc(), others will call __delay() directly. Note: regard 4G as the max CPU frequence of current single CPU. Signed-off-by: Dou Liyang --- arch/x86/kernel/apic/io_apic.c | 45 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 237e9c2..348ea7e 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1585,6 +1585,43 @@ static int __init notimercheck(char *s) } __setup("no_timer_check", notimercheck); +static void __init delay_with_tsc(void) +{ + unsigned long long start, now; + unsigned long end = jiffies + 4; + + start = rdtsc(); + + /* + * We don't know the TSC frequency yet, but waiting for + * 40000000000/HZ TSC cycles is safe: + * 4 GHz == 10 jiffies + * 1 GHz == 40 jiffies + */ + do { + rep_nop(); + now = rdtsc(); + } while ((now - start) < 40000000000UL / HZ && + time_before_eq(jiffies, end)); +} + +static void __init delay_without_tsc(void) +{ + unsigned long end = jiffies + 4; + int band = 1; + + /* + * We don't know any frequency yet, but waiting for + * 40940000000/HZ cycles is safe: + * 4 GHz == 10 jiffies + * 1 GHz == 40 jiffies + * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094 + */ + do { + __delay(((1U << band++) * 10000000UL) / HZ); + } while (band < 12 && time_before_eq(jiffies, end)); +} + /* * There is a nasty bug in some older SMP boards, their mptable lies * about the timer IRQ. We do the following to work around the situation: @@ -1603,8 +1640,12 @@ static int __init timer_irq_works(void) local_save_flags(flags); local_irq_enable(); - /* Let ten ticks pass... */ - mdelay((10 * 1000) / HZ); + + if (boot_cpu_has(X86_FEATURE_TSC)) + delay_with_tsc(); + else + delay_without_tsc(); + local_irq_restore(flags); /* -- 2.5.5