From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751203AbdH1Gdu (ORCPT ); Mon, 28 Aug 2017 02:33:50 -0400 Received: from olimex.com ([184.105.72.32]:59321 "EHLO olimex.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751177AbdH1Gds (ORCPT ); Mon, 28 Aug 2017 02:33:48 -0400 From: Stefan Mavrodiev To: Rob Herring , Mark Rutland , Russell King , Maxime Ripard , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Stefan Mavrodiev , linux-sunxi@googlegroups.com Subject: [PATCH v2 1/2] ARM: dts: sun7i: Fix A20-OLinuXino-MICRO dts for LAN8710 Date: Mon, 28 Aug 2017 09:32:42 +0300 Message-Id: <1503901963-9457-2-git-send-email-stefan@olimex.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503901963-9457-1-git-send-email-stefan@olimex.com> References: <1503901963-9457-1-git-send-email-stefan@olimex.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >>From revision J the board uses new phy chip LAN8710. Compared with RTL8201, RA17 pin is TXERR. It has pullup which causes phy not to work. To fix this PA17 is muxed with GMAC function. This makes the pin output-low. This patch is compatible with earlier board revisions, since this pin wasn't connected to phy. Signed-off-by: Stefan Mavrodiev --- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 0b7403e..cb1b081 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -102,7 +102,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_pins_mii_a>,<&gmac_txerr>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -229,6 +229,11 @@ }; &pio { + gmac_txerr: gmac_txerr@0 { + pins = "PA17"; + function = "gmac"; + }; + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { pins = "PH11"; function = "gpio_in"; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: stefan@olimex.com (Stefan Mavrodiev) Date: Mon, 28 Aug 2017 09:32:42 +0300 Subject: [PATCH v2 1/2] ARM: dts: sun7i: Fix A20-OLinuXino-MICRO dts for LAN8710 In-Reply-To: <1503901963-9457-1-git-send-email-stefan@olimex.com> References: <1503901963-9457-1-git-send-email-stefan@olimex.com> Message-ID: <1503901963-9457-2-git-send-email-stefan@olimex.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org >>From revision J the board uses new phy chip LAN8710. Compared with RTL8201, RA17 pin is TXERR. It has pullup which causes phy not to work. To fix this PA17 is muxed with GMAC function. This makes the pin output-low. This patch is compatible with earlier board revisions, since this pin wasn't connected to phy. Signed-off-by: Stefan Mavrodiev --- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 0b7403e..cb1b081 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -102,7 +102,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_pins_mii_a>,<&gmac_txerr>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -229,6 +229,11 @@ }; &pio { + gmac_txerr: gmac_txerr at 0 { + pins = "PA17"; + function = "gmac"; + }; + mmc3_cd_pin_olinuxinom: mmc3_cd_pin at 0 { pins = "PH11"; function = "gpio_in"; -- 2.7.4