From mboxrd@z Thu Jan 1 00:00:00 1970 From: tien.fong.chee at intel.com Date: Tue, 29 Aug 2017 18:45:53 +0800 Subject: [U-Boot] [PATCH 11/19] arm: socfpga: Enable build for DDR Arria 10 In-Reply-To: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com> References: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com> Message-ID: <1504003561-6290-12-git-send-email-tien.fong.chee@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Tien Fong Chee This patch is for enabling the DDR support on Arria 10. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/Makefile | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index ac4ab85..02f8b7c 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -10,4 +10,5 @@ ifdef CONFIG_ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o endif -- 1.7.7.4