From mboxrd@z Thu Jan 1 00:00:00 1970 From: tien.fong.chee at intel.com Date: Tue, 29 Aug 2017 18:45:57 +0800 Subject: [U-Boot] [PATCH 15/19] arm: socfpga: Add support to memory allocation in SPL In-Reply-To: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com> References: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com> Message-ID: <1504003561-6290-16-git-send-email-tien.fong.chee@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Tien Fong Chee Add support to memory allocation in SPL for preparation to enable FAT in SPL. Memory allocation is needed by FAT to work properly. Signed-off-by: Tien Fong Chee --- include/configs/socfpga_common.h | 23 ++++++++++++++++++++++- 1 files changed, 22 insertions(+), 1 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 05b03bd..0f53888 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -292,17 +292,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * SPL * - * SRAM Memory layout: + * SRAM Memory layout for gen 5: * * 0xFFFF_0000 ...... Start of SRAM * 0xFFFF_xxxx ...... Top of stack (grows down) * 0xFFFF_yyyy ...... Malloc area * 0xFFFF_zzzz ...... Global Data * 0xFFFF_FF00 ...... End of SRAM + * + * SRAM Memory layout for Arria 10: + * 0xFFE0_0000 ...... Start of SRAM (bottom) + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) + * 0xFFEy_yyyy ...... Malloc area (grows up to top) + * 0xFFEz_zzzz ...... Global Data + * 0xFFE3_FFFF ...... End of SRAM (top) */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +/* SPL memory allocation configuration, it is required by FAT feature */ +#ifndef CONFIG_SYS_SPL_MALLOC_START +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00002000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE + \ + CONFIG_SYS_INIT_RAM_ADDR) +#endif +#endif /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT @@ -332,7 +349,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * Stack setup */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START - 1) +#endif /* Extra Environment */ #ifndef CONFIG_SPL_BUILD -- 1.7.7.4