Re: [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue

["Vivi, Rodrigo" <rodrigo.vivi@intel.com>]

On Tue, 2017-08-29 at 09:42 +0300, Jani Nikula wrote:
> On Tue, 29 Aug 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > This workaround fixes a CNL PCH bug when changing
> > backlight from a lower frequency to a higher frequency.
> >
> > During random reboot cycles, display backlight seems to
> > be off/ dim for 2-3 mins.
> >
> > The only functional change on this patch is to
> > set bit 13 of 0xC2020 for CNL PCH.
> >
> > The rest of patch is organizing identation around
> > those bits definitions and re-organizing CFL workarounds.
> >
> > Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 11 ++++++-----
> >  drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++--
> >  2 files changed, 31 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c59c590e45c4..31b1b1dfb754 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7474,11 +7474,12 @@ enum {
> >  #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
> >  #define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
> >  
> > -#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
> > -#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
> > -#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
> > -#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> > -#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
> > +#define SOUTH_DSPCLK_GATE_D			_MMIO(0xc2020)
> > +#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE		(1<<30)
> > +#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE	(1<<29)
> > +#define  PCH_CPUNIT_CLOCK_GATE_DISABLE		(1<<14)
> > +#define  CNP_PWM_CGE_GATING_DISABLE		(1<<13)
> 
> Only add this one line, please don't reshuffle the rest.

yep... my momentary OCD took over and fixed indentation around what I
was touching to avoid extra patch...

> 
> > +#define  PCH_LP_PARTITION_LEVEL_DISABLE		(1<<12)
> >  
> >  /* CPU: FDI_TX */
> >  #define _FDI_TXA_CTL            0x60100
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 88bbbc44c00d..5a4b41ea0c3a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> >  	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> >  }
> >  
> > +static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> > +{
> > +	if (!HAS_PCH_CNP(dev_priv))
> > +		return;
> 
> Is this for CFL without CNP?

Nope. CNP only.

So far we have CFL with KBP and CNP
and we have CNL with CNP but who know what we might have in the future,
so I preferred to skip inside the function instead of adding 2 ifs
outside and/or have to fix it later.

> 
> BR,
> Jani.
> 
> > +
> > +	/* Wa #1181 */
> > +	I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
> > +}
> > +
> >  static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> > +	cnp_init_clock_gating(dev_priv);
> > +
> >  	/* This is not an Wa. Enable for better image quality */
> >  	I915_WRITE(_3D_CHICKEN3,
> >  		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> > @@ -8285,6 +8296,16 @@ static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  			   SARBUNIT_CLKGATE_DIS);
> >  }
> >  
> > +static void coffeelake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +{
> > +	cnp_init_clock_gating(dev_priv);
> > +	gen9_init_clock_gating(dev_priv);
> > +
> > +	/* WaFbcNukeOnHostModify:cfl */
> > +	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> > +		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> > +}
> > +
> >  static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  {
> >  	gen9_init_clock_gating(dev_priv);
> > @@ -8299,7 +8320,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> >  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> >  
> > -	/* WaFbcNukeOnHostModify:kbl,cfl */
> > +	/* WaFbcNukeOnHostModify:kbl */
> >  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >  }
> > @@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> >  {
> >  	if (IS_CANNONLAKE(dev_priv))
> >  		dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
> > +	else if (IS_COFFEELAKE(dev_priv))
> > +		dev_priv->display.init_clock_gating = coffeelake_init_clock_gating;
> >  	else if (IS_SKYLAKE(dev_priv))
> >  		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> > -	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> > +	else if (IS_KABYLAKE(dev_priv))
> >  		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
> >  	else if (IS_BROXTON(dev_priv))
> >  		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> 

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