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From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2] mtd/spi: Add MT35XU512ABA1G12 NOR flash support
Date: Thu, 31 Aug 2017 17:50:19 +0530	[thread overview]
Message-ID: <1504182019-2047-1-git-send-email-yogeshnarayan.gaur@nxp.com> (raw)

Add MT35XU512ABA1G12 parameters to NOR flash parameters array.

The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
---
Change in v2:
 - Incorporated Jagan's review comments. Removed macro SPI_FLASH_CFI_MFR_MICRON
---
 drivers/mtd/spi/spi_flash_ids.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index c4ccf48..e4f4570 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -134,6 +134,7 @@ const struct spi_flash_info spi_flash_ids[] = {
 	{"n25q1024a",	   INFO(0x20bb21, 0x0,  64 * 1024,  2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
 	{"mt25qu02g",	   INFO(0x20bb22, 0x0,  64 * 1024,  4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
 	{"mt25ql02g",	   INFO(0x20ba22, 0x0,  64 * 1024,  4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+	{"mt35xu512g",	   INFO6(0x2c5b1a, 0x104100,  128 * 1024,  512, E_FSR | SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_SST		/* SST */
 	{"sst25vf040b",	   INFO(0xbf258d, 0x0,	64 * 1024,     8, SECT_4K | SST_WR) },
-- 
1.9.1

             reply	other threads:[~2017-08-31 12:20 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-31 12:20 Yogesh Gaur [this message]
  -- strict thread matches above, loose matches on Subject: below --
2017-08-31  4:56 [U-Boot] [PATCH v2] mtd/spi: Add MT35XU512ABA1G12 NOR flash support Yogesh Gaur
2017-08-31 14:13 ` Jagan Teki
2017-09-25  7:21   ` Jagan Teki

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