From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 00/33] target-arm queue
Date: Mon, 4 Sep 2017 17:21:15 +0100 [thread overview]
Message-ID: <1504542075-28447-1-git-send-email-peter.maydell@linaro.org> (raw)
Third time's the charm...
-- PMM
The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-2
for you to fetch changes up to 7229ec5825df6b933f150b54a8a2bedd2de1864c:
arm_gicv3_kvm: Fix compile warning (2017-09-04 17:13:53 +0100)
----------------------------------------------------------------
target-arm:
* collection of M profile cleanups and minor bugfixes
* loader: handle ELF files with overlapping zero-init data
* virt: allow PMU instantiation with userspace irqchip
* wdt_aspeed: Add support for the reset width register
* cpu: Define new cpu_transaction_failed() hook
* Mark some SoC devices as not user-creatable
* arm: Fix aa64 ldp register writeback
* arm_gicv3_kvm: Fix compile warning
----------------------------------------------------------------
Andrew Jeffery (2):
watchdog: wdt_aspeed: Add support for the reset width register
aspeed_soc: Propagate silicon-rev to watchdog
Andrew Jones (4):
hw/arm/virt: add pmu interrupt state
target/arm/kvm: pmu: split init and set-irq stages
hw/arm/virt: allow pmu instantiation with userspace irqchip
target/arm/kvm: pmu: improve error handling
Peter Maydell (22):
target/arm: Use MMUAccessType enum rather than int
target/arm: Don't trap WFI/WFE for M profile
target/arm: Consolidate PMSA handling in get_phys_addr()
target/arm: Tighten up Thumb decode where new v8M insns will be
hw/intc/armv7m_nvic.c: Remove out of date comment
target/arm: Remove incorrect comment about MPU_CTRL
target/arm: Fix outdated comment about exception exit
target/arm: Define and use XPSR bit masks
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
target/arm: Create and use new function arm_v7m_is_handler_mode()
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
nvic: Implement "user accesses BusFault" SCS region behaviour
loader: Handle ELF files with overlapping zero-initialized data
loader: Ignore zero-sized ELF segments
memory.h: Move MemTxResult type to memattrs.h
cpu: Define new cpu_transaction_failed() hook
cputlb: Support generating CPU exceptions on memory transaction failures
target/arm: Factor out fault delivery code
target/arm: Allow deliver_fault() caller to specify EA bit
Philippe Mathieu-Daudé (1):
hw/arm: use defined type name instead of hard-coded string
Pranith Kumar (1):
arm_gicv3_kvm: Fix compile warning
Richard Henderson (1):
target/arm: Fix aa64 ldp register writeback
Thomas Huth (2):
hw/arm/aspeed_soc: Mark devices as user_creatable = false
hw/arm/digic: Mark device with user_creatable = false
include/exec/memattrs.h | 10 +++
include/exec/memory.h | 10 ---
include/hw/arm/armv7m.h | 2 +-
include/hw/elf_ops.h | 72 +++++++++++++++++--
include/hw/{arm => intc}/armv7m_nvic.h | 0
include/hw/watchdog/wdt_aspeed.h | 2 +
include/qom/cpu.h | 22 ++++++
softmmu_template.h | 4 +-
target/arm/cpu.h | 56 +++++++++++----
target/arm/internals.h | 5 +-
target/arm/kvm_arm.h | 9 ++-
accel/tcg/cputlb.c | 32 ++++++++-
hw/arm/armv7m.c | 4 +-
hw/arm/aspeed_soc.c | 4 ++
hw/arm/digic.c | 2 +
hw/arm/exynos4210.c | 4 +-
hw/arm/highbank.c | 11 +--
hw/arm/realview.c | 6 +-
hw/arm/vexpress.c | 6 +-
hw/arm/virt.c | 12 +++-
hw/arm/xilinx_zynq.c | 14 ++--
hw/intc/arm_gicv3_kvm.c | 2 +-
hw/intc/armv7m_nvic.c | 68 +++++++++++-------
hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++++++++---
target/arm/cpu.c | 7 +-
target/arm/helper.c | 124 ++++++++++++++++-----------------
target/arm/kvm.c | 6 +-
target/arm/kvm32.c | 8 ++-
target/arm/kvm64.c | 63 ++++++++++-------
target/arm/machine.c | 54 +++++++++++++-
target/arm/op_helper.c | 121 +++++++++++++++++---------------
target/arm/translate-a64.c | 29 ++++----
target/arm/translate.c | 106 +++++++++++++++++++++-------
33 files changed, 677 insertions(+), 291 deletions(-)
rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
next reply other threads:[~2017-09-04 16:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-04 16:21 Peter Maydell [this message]
2017-09-04 17:28 ` [Qemu-devel] [PULL 00/33] target-arm queue Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2018-10-08 13:59 Peter Maydell
2018-10-08 14:46 ` Peter Maydell
2014-12-11 12:19 Peter Maydell
2014-12-11 18:26 ` Peter Maydell
2012-06-20 12:26 Peter Maydell
2012-06-24 12:27 ` Blue Swirl
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1504542075-28447-1-git-send-email-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.