All of lore.kernel.org
 help / color / mirror / Atom feed
From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA
Date: Wed, 6 Sep 2017 07:15:33 +0000	[thread overview]
Message-ID: <1504682132.7727.123.camel@intel.com> (raw)
In-Reply-To: <a045c7f5-5bd2-74a1-b469-5a7760b2deca@denx.de>

On Rab, 2017-09-06 at 09:10 +0200, Marek Vasut wrote:
> On 09/06/2017 07:06 AM, Chee, Tien Fong wrote:
> [...]
> > 
> > > 
> > > > 
> > > > > 
> > > > > > 
> > > > > > The BSP tool is used to describe internal FPGA in SOCFPGA.
> > > > > > Other
> > > > > > external FPGAs other than SOCFPGA itself, it can be
> > > > > > programmed
> > > > > > through
> > > > > > U-boot.
> > > > > The BSP tool is broken if it generates broken DT, do I have
> > > > > to
> > > > > repeat
> > > > > myself ?
> > > > > 
> > > > BSP tool is only generate the RBF filename for FPGA inside
> > > > SOCFPGA.
> > > > Multiple external FPGA are configured through U-boot.
> > > What happens if you have FPGA connector over SPI ?
> > > 
> > I assume you are saying FPGA connected to EPCQ
> No, I mean FPGA connected over SPI bus.
> 
> > 
> > , and this is one of the
> > external FPGA configuration, like PCIE. For any external FPGA
> > configuration, FPGA itself/external HOST would get the FPGA data
> > from
> > storage such as EPCQ and configuring the FPGA without
> > HPS/Bootloader
> > intervine. SPL/U-boot would skip the FPGA configuration process
> > when
> > they see the mode is set to external FPGA configuration.
> > 
> > I know you want a DT to describe all FPGAs with FPGA node and their
> > own
> > data filename in every node. But, at this moment, all external
> > FPGAs
> > chip other than SOCFPGA itself are configured through U-boot(script 
> > &
> > env variable), or external FPGA configuration method.
> I want DT which describes hardware and is not misdesigned crap.
> Just because the BSP tool is broken does not mean I can allow
> upstream
> to accept that, no way.
> 
> > 
> > How about i just create a FPGA node for SOCFPGA, with FPGA data
> > filename within the node?
> Isn't that what the FPGA manager in mainline Linux does already ?
> 
Yeah, i will port from Linux DTS, and filenames added into the node.

  reply	other threads:[~2017-09-06  7:15 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-29 10:45 [U-Boot] [PATCH 00/19] Add FPGA, SDRAM drivers and booting to U-boot tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 01/19] configs: Add FPGA loadfs config for Arria 10 tien.fong.chee at intel.com
2017-08-29 11:51   ` Marek Vasut
2017-08-30  5:59     ` Chee, Tien Fong
2017-08-30  8:45       ` Marek Vasut
2017-09-04  5:29         ` Chee, Tien Fong
2017-08-29 10:45 ` [U-Boot] [PATCH 02/19] configs: Add FAT fs support for SPL tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA tien.fong.chee at intel.com
2017-08-29 11:55   ` Marek Vasut
2017-08-30  8:05     ` Chee, Tien Fong
2017-08-30  8:52       ` Marek Vasut
2017-09-04  7:08         ` Chee, Tien Fong
2017-09-04  9:39           ` Marek Vasut
2017-09-05  5:53             ` Chee, Tien Fong
2017-09-05  9:04               ` Marek Vasut
2017-09-05  9:23                 ` Chee, Tien Fong
2017-09-05  9:36                   ` Marek Vasut
2017-09-06  5:06                     ` Chee, Tien Fong
2017-09-06  7:10                       ` Marek Vasut
2017-09-06  7:15                         ` Chee, Tien Fong [this message]
2017-08-29 10:45 ` [U-Boot] [PATCH 04/19] arm: socfpga: Add FPGA loadfs command support tien.fong.chee at intel.com
2017-08-29 11:57   ` Marek Vasut
2017-08-30  8:18     ` Chee, Tien Fong
2017-08-30  8:54       ` Marek Vasut
2017-08-29 10:45 ` [U-Boot] [PATCH 05/19] arm: socfpga: Enhance FPGA program support with at least 4 byte data tien.fong.chee at intel.com
2017-08-29 11:58   ` Marek Vasut
2017-08-30  8:24     ` Chee, Tien Fong
2017-08-30  8:55       ` Marek Vasut
2017-09-04  7:09         ` Chee, Tien Fong
2017-08-29 10:45 ` [U-Boot] [PATCH 06/19] arm: socfpga: Rename the gen5 sdram driver to more specific name tien.fong.chee at intel.com
2017-08-29 11:59   ` Marek Vasut
2017-08-30  8:26     ` Chee, Tien Fong
2017-08-29 10:45 ` [U-Boot] [PATCH 07/19] arm: socfpga: Add DRAM bank size initialization function tien.fong.chee at intel.com
2017-08-29 11:59   ` Marek Vasut
2017-08-30  8:36     ` Chee, Tien Fong
2017-08-30  8:56       ` Marek Vasut
2017-09-04  7:11         ` Chee, Tien Fong
2017-09-04  9:40           ` Marek Vasut
2017-09-05  3:54             ` Chee, Tien Fong
2017-08-29 10:45 ` [U-Boot] [PATCH 08/19] arm: socfpga: Add COMPAT macro for Network on Chip(NoC) tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 09/19] arm: socfpga: Add DDR driver for Arria 10 tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 10/19] configs: Add DDR Kconfig support " tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 11/19] arm: socfpga: Enable build for DDR " tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 12/19] doc: dtbinding: Add Intel Arria 10 SoCFPGA chosen binding tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 13/19] dts: Add the FPGA design file name to DTS tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 14/19] dts: Add device storage and partition " tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 15/19] arm: socfpga: Add support to memory allocation in SPL tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 17/19] arm: socfpga: Adding clock frequency info for U-boot tien.fong.chee at intel.com
2017-08-29 10:46 ` [U-Boot] [PATCH 18/19] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot tien.fong.chee at intel.com
2017-08-29 10:46 ` [U-Boot] [PATCH 19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot tien.fong.chee at intel.com

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1504682132.7727.123.camel@intel.com \
    --to=tien.fong.chee@intel.com \
    --cc=u-boot@lists.denx.de \
    --subject='Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.