[PATCH 0/3] drm/i915: Skylake plane update/disable unifications [v3]

[PATCH 0/3] drm/i915: Skylake plane update/disable unifications [v3]

[Juha-Pekka Heikkila]

[v3] Took into account fbc adjusted y/x for primary plane (ville syrjälä)

[v2] Fixed missed references which were brough on rebase.

/Juha-Pekka

Juha-Pekka Heikkila (3):
  drm/i915: dspaddr_offset doesn't need to be more than local variable
  drm/i915: Unify skylake plane update
  drm/i915: Unify skylake plane disable

 drivers/gpu/drm/i915/i915_drv.h      |   8 +++
 drivers/gpu/drm/i915/intel_display.c | 117 +++--------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |  11 ++--
 drivers/gpu/drm/i915/intel_fbc.c     |  11 +++-
 drivers/gpu/drm/i915/intel_sprite.c  |   4 +-
 5 files changed, 32 insertions(+), 119 deletions(-)

-- 
2.7.4

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[PATCH 1/3] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Juha-Pekka Heikkila]

Move u32 dspaddr_offset from struct intel_crtc member into local
variable in i9xx_update_primary_plane()

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
 drivers/gpu/drm/i915/intel_drv.h     |  1 -
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7cd392f..f922e2f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3287,13 +3287,14 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	int x = plane_state->main.x;
 	int y = plane_state->main.y;
 	unsigned long irqflags;
+	u32 dspaddr_offset;
 
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (INTEL_GEN(dev_priv) >= 4)
-		crtc->dspaddr_offset = plane_state->main.offset;
+		dspaddr_offset = plane_state->main.offset;
 	else
-		crtc->dspaddr_offset = linear_offset;
+		dspaddr_offset = linear_offset;
 
 	crtc->adjusted_x = x;
 	crtc->adjusted_y = y;
@@ -3322,18 +3323,18 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
 		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
 	} else {
 		I915_WRITE_FW(DSPADDR(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 	}
 	POSTING_READ_FW(reg);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 17649f1..0d0abed1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -805,7 +805,6 @@ struct intel_crtc {
 	/* Display surface base address adjustement for pageflips. Note that on
 	 * gen4+ this only adjusts up to a tile, offsets within a tile are
 	 * handled in the hw itself (with the TILEOFF register). */
-	u32 dspaddr_offset;
 	int adjusted_x;
 	int adjusted_y;
 
-- 
2.7.4

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[PATCH 2/3] drm/i915: Unify skylake plane update

[Juha-Pekka Heikkila]

Don't handle skylake primary plane separately as it is similar
plane as the others.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  8 ++++
 drivers/gpu/drm/i915/intel_display.c | 85 +-----------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |  9 ++--
 drivers/gpu/drm/i915/intel_fbc.c     | 11 +++--
 drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
 5 files changed, 22 insertions(+), 93 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8352cbe..2f96286 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1077,6 +1077,14 @@ struct intel_fbc {
 			int src_w;
 			int src_h;
 			bool visible;
+			/*
+			 * Display surface base address adjustement for
+			 * pageflips. Note that on gen4+ this only adjusts up
+			 * to a tile, offsets within a tile are handled in
+			 * the hw itself (with the TILEOFF register).
+			 */
+			int adjusted_x;
+			int adjusted_y;
 		} plane;
 
 		struct {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f922e2f..ac4073a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3278,7 +3278,6 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 				      const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	enum plane plane = primary->plane;
 	u32 linear_offset;
@@ -3296,9 +3295,6 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	else
 		dspaddr_offset = linear_offset;
 
-	crtc->adjusted_x = x;
-	crtc->adjusted_y = y;
-
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	if (INTEL_GEN(dev_priv) < 4) {
@@ -3534,83 +3530,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 	return plane_ctl;
 }
 
-static void skylake_update_primary_plane(struct intel_plane *plane,
-					 const struct intel_crtc_state *crtc_state,
-					 const struct intel_plane_state *plane_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	enum plane_id plane_id = plane->id;
-	enum pipe pipe = plane->pipe;
-	u32 plane_ctl = plane_state->ctl;
-	unsigned int rotation = plane_state->base.rotation;
-	u32 stride = skl_plane_stride(fb, 0, rotation);
-	u32 aux_stride = skl_plane_stride(fb, 1, rotation);
-	u32 surf_addr = plane_state->main.offset;
-	int scaler_id = plane_state->scaler_id;
-	int src_x = plane_state->main.x;
-	int src_y = plane_state->main.y;
-	int src_w = drm_rect_width(&plane_state->base.src) >> 16;
-	int src_h = drm_rect_height(&plane_state->base.src) >> 16;
-	int dst_x = plane_state->base.dst.x1;
-	int dst_y = plane_state->base.dst.y1;
-	int dst_w = drm_rect_width(&plane_state->base.dst);
-	int dst_h = drm_rect_height(&plane_state->base.dst);
-	unsigned long irqflags;
-
-	/* Sizes are 0 based */
-	src_w--;
-	src_h--;
-	dst_w--;
-	dst_h--;
-
-	crtc->dspaddr_offset = surf_addr;
-
-	crtc->adjusted_x = src_x;
-	crtc->adjusted_y = src_y;
-
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
-	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
-			      PLANE_COLOR_PIPE_GAMMA_ENABLE |
-			      PLANE_COLOR_PIPE_CSC_ENABLE |
-			      PLANE_COLOR_PLANE_GAMMA_DISABLE);
-	}
-
-	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
-	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
-	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
-	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
-		      (plane_state->aux.offset - surf_addr) | aux_stride);
-	I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
-		      (plane_state->aux.y << 16) | plane_state->aux.x);
-
-	if (scaler_id >= 0) {
-		uint32_t ps_ctrl = 0;
-
-		WARN_ON(!dst_w || !dst_h);
-		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
-			crtc_state->scaler_state.scalers[scaler_id].mode;
-		I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
-		I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
-		I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
-		I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
-		I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
-	} else {
-		I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
-	}
-
-	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
-		      intel_plane_ggtt_offset(plane_state) + surf_addr);
-
-	POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
-
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-}
-
 static void skylake_disable_primary_plane(struct intel_plane *primary,
 					  struct intel_crtc *crtc)
 {
@@ -13265,7 +13184,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		num_formats = ARRAY_SIZE(skl_primary_formats);
 		modifiers = skl_format_modifiers_ccs;
 
-		primary->update_plane = skylake_update_primary_plane;
+		primary->update_plane = skl_update_plane;
 		primary->disable_plane = skylake_disable_primary_plane;
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		intel_primary_formats = skl_primary_formats;
@@ -13275,7 +13194,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		else
 			modifiers = skl_format_modifiers_noccs;
 
-		primary->update_plane = skylake_update_primary_plane;
+		primary->update_plane = skl_update_plane;
 		primary->disable_plane = skylake_disable_primary_plane;
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		intel_primary_formats = i965_primary_formats;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0d0abed1..d932613 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -802,12 +802,6 @@ struct intel_crtc {
 	unsigned long long enabled_power_domains;
 	struct intel_overlay *overlay;
 
-	/* Display surface base address adjustement for pageflips. Note that on
-	 * gen4+ this only adjusts up to a tile, offsets within a tile are
-	 * handled in the hw itself (with the TILEOFF register). */
-	int adjusted_x;
-	int adjusted_y;
-
 	struct intel_crtc_state *config;
 
 	/* global reset count when the last flip was submitted */
@@ -1887,6 +1881,9 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 			      struct drm_file *file_priv);
 void intel_pipe_update_start(struct intel_crtc *crtc);
 void intel_pipe_update_end(struct intel_crtc *crtc);
+void skl_update_plane(struct intel_plane *plane,
+		      const struct intel_crtc_state *crtc_state,
+		      const struct intel_plane_state *plane_state);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 58a772d..dc059808 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -71,7 +71,10 @@ static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  */
 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
 {
-	return crtc->base.y - crtc->adjusted_y;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_fbc *fbc = &dev_priv->fbc;
+
+	return crtc->base.y - fbc->state_cache.plane.adjusted_y;
 }
 
 /*
@@ -727,8 +730,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 
 	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 					&effective_h);
-	effective_w += crtc->adjusted_x;
-	effective_h += crtc->adjusted_y;
+	effective_w += fbc->state_cache.plane.adjusted_x;
+	effective_h += fbc->state_cache.plane.adjusted_y;
 
 	return effective_w <= max_w && effective_h <= max_h;
 }
@@ -757,6 +760,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 	cache->plane.visible = plane_state->base.visible;
+	cache->plane.adjusted_x = plane_state->main.x;
+	cache->plane.adjusted_y = plane_state->main.y;
 
 	if (!cache->plane.visible)
 		return;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 524933b..ef16519 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -225,7 +225,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc)
 #endif
 }
 
-static void
+void
 skl_update_plane(struct intel_plane *plane,
 		 const struct intel_crtc_state *crtc_state,
 		 const struct intel_plane_state *plane_state)
-- 
2.7.4

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[PATCH 3/3] drm/i915: Unify skylake plane disable

[Juha-Pekka Heikkila]

Don't handle skylake primary plane separately as it is similar
plane as the others.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 21 ++-------------------
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
 3 files changed, 4 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ac4073a..17fe6f2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3530,23 +3530,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 	return plane_ctl;
 }
 
-static void skylake_disable_primary_plane(struct intel_plane *primary,
-					  struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-	enum plane_id plane_id = primary->id;
-	enum pipe pipe = primary->pipe;
-	unsigned long irqflags;
-
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
-	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
-	I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
-	POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
-
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-}
-
 static int
 __intel_display_resume(struct drm_device *dev,
 		       struct drm_atomic_state *state,
@@ -13185,7 +13168,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		modifiers = skl_format_modifiers_ccs;
 
 		primary->update_plane = skl_update_plane;
-		primary->disable_plane = skylake_disable_primary_plane;
+		primary->disable_plane = skl_disable_plane;
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		intel_primary_formats = skl_primary_formats;
 		num_formats = ARRAY_SIZE(skl_primary_formats);
@@ -13195,7 +13178,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 			modifiers = skl_format_modifiers_noccs;
 
 		primary->update_plane = skl_update_plane;
-		primary->disable_plane = skylake_disable_primary_plane;
+		primary->disable_plane = skl_disable_plane;
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		intel_primary_formats = i965_primary_formats;
 		num_formats = ARRAY_SIZE(i965_primary_formats);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d932613..cb44a51 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1884,6 +1884,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc);
 void skl_update_plane(struct intel_plane *plane,
 		      const struct intel_crtc_state *crtc_state,
 		      const struct intel_plane_state *plane_state);
+void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index ef16519..bc6bae6 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -306,7 +306,7 @@ skl_update_plane(struct intel_plane *plane,
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static void
+void
 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-- 
2.7.4

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✗ Fi.CI.BAT: failure for drm/i915: Skylake plane update/disable unifications [v3]

[Patchwork]

== Series Details ==

Series: drm/i915: Skylake plane update/disable unifications [v3]
URL   : https://patchwork.freedesktop.org/series/30122/
State : failure

== Summary ==

  CHK     include/config/kernel.release
  CHK     include/generated/uapi/linux/version.h
  CHK     include/generated/utsrelease.h
  CHK     include/generated/bounds.h
  CHK     include/generated/timeconst.h
  CHK     include/generated/asm-offsets.h
  CALL    scripts/checksyscalls.sh
  CHK     scripts/mod/devicetable-offsets.h
  CHK     include/generated/compile.h
  CHK     kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_drv.o
In file included from drivers/gpu/drm/i915/i915_trace.h:10:0,
                 from drivers/gpu/drm/i915/i915_drv.h:3194,
                 from drivers/gpu/drm/i915/i915_drv.c:49:
drivers/gpu/drm/i915/intel_drv.h:1913:1: error: version control conflict marker in file
 <<<<<<< HEAD
 ^~~~~~~
drivers/gpu/drm/i915/intel_drv.h:1916:1: error: version control conflict marker in file
 =======
 ^~~~~~~
drivers/gpu/drm/i915/intel_drv.h:1918:6: error: conflicting types for ‘intel_pipe_update_end’
 void intel_pipe_update_end(struct intel_crtc *crtc);
      ^~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_drv.h:1915:6: note: previous declaration of ‘intel_pipe_update_end’ was here
 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
      ^~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_drv.h:1922:1: error: version control conflict marker in file
 >>>>>>> drm/i915: Unify skylake plane update
 ^~~~~~~
scripts/Makefile.build:302: recipe for target 'drivers/gpu/drm/i915/i915_drv.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_drv.o] Error 1
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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Re: [PATCH 1/3] drm/i915: dspaddr_offset doesn't need to be more than local variable

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 8003 bytes --]

Hi Juha-Pekka,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.13 next-20170914]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Juha-Pekka-Heikkila/drm-i915-Skylake-plane-update-disable-unifications-v3/20170914-112949
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x013-201737 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

Note: the linux-review/Juha-Pekka-Heikkila/drm-i915-Skylake-plane-update-disable-unifications-v3/20170914-112949 HEAD 64d427ba0647f6bc6a228cf54d16f757633c98e6 builds fine.
      It only hurts bisectibility.

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_display.c: In function 'skylake_update_primary_plane':
>> drivers/gpu/drm/i915/intel_display.c:3588:6: error: 'struct intel_crtc' has no member named 'dspaddr_offset'; did you mean 'scanline_offset'?
     crtc->dspaddr_offset = surf_addr;
         ^~

vim +3588 drivers/gpu/drm/i915/intel_display.c

46f788ba2 Ville Syrjälä     2017-03-17  3556  
282dbf9b0 Ville Syrjälä     2017-03-27  3557  static void skylake_update_primary_plane(struct intel_plane *plane,
a8d201af6 Maarten Lankhorst 2016-01-07  3558  					 const struct intel_crtc_state *crtc_state,
a8d201af6 Maarten Lankhorst 2016-01-07  3559  					 const struct intel_plane_state *plane_state)
6156a4560 Chandra Konduru   2015-04-27  3560  {
282dbf9b0 Ville Syrjälä     2017-03-27  3561  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
282dbf9b0 Ville Syrjälä     2017-03-27  3562  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
282dbf9b0 Ville Syrjälä     2017-03-27  3563  	const struct drm_framebuffer *fb = plane_state->base.fb;
282dbf9b0 Ville Syrjälä     2017-03-27  3564  	enum plane_id plane_id = plane->id;
282dbf9b0 Ville Syrjälä     2017-03-27  3565  	enum pipe pipe = plane->pipe;
a0864d590 Ville Syrjälä     2017-03-23  3566  	u32 plane_ctl = plane_state->ctl;
a8d201af6 Maarten Lankhorst 2016-01-07  3567  	unsigned int rotation = plane_state->base.rotation;
d21967740 Ville Syrjälä     2016-01-28  3568  	u32 stride = skl_plane_stride(fb, 0, rotation);
2e2adb057 Ville Syrjälä     2017-08-01  3569  	u32 aux_stride = skl_plane_stride(fb, 1, rotation);
b63a16f6c Ville Syrjälä     2016-01-28  3570  	u32 surf_addr = plane_state->main.offset;
a8d201af6 Maarten Lankhorst 2016-01-07  3571  	int scaler_id = plane_state->scaler_id;
b63a16f6c Ville Syrjälä     2016-01-28  3572  	int src_x = plane_state->main.x;
b63a16f6c Ville Syrjälä     2016-01-28  3573  	int src_y = plane_state->main.y;
936e71e31 Ville Syrjälä     2016-07-26  3574  	int src_w = drm_rect_width(&plane_state->base.src) >> 16;
936e71e31 Ville Syrjälä     2016-07-26  3575  	int src_h = drm_rect_height(&plane_state->base.src) >> 16;
936e71e31 Ville Syrjälä     2016-07-26  3576  	int dst_x = plane_state->base.dst.x1;
936e71e31 Ville Syrjälä     2016-07-26  3577  	int dst_y = plane_state->base.dst.y1;
936e71e31 Ville Syrjälä     2016-07-26  3578  	int dst_w = drm_rect_width(&plane_state->base.dst);
936e71e31 Ville Syrjälä     2016-07-26  3579  	int dst_h = drm_rect_height(&plane_state->base.dst);
dd584fc07 Ville Syrjälä     2017-03-09  3580  	unsigned long irqflags;
70d21f0e9 Damien Lespiau    2013-07-03  3581  
6687c9062 Ville Syrjälä     2015-09-15  3582  	/* Sizes are 0 based */
6687c9062 Ville Syrjälä     2015-09-15  3583  	src_w--;
6687c9062 Ville Syrjälä     2015-09-15  3584  	src_h--;
6687c9062 Ville Syrjälä     2015-09-15  3585  	dst_w--;
6687c9062 Ville Syrjälä     2015-09-15  3586  	dst_h--;
6687c9062 Ville Syrjälä     2015-09-15  3587  
282dbf9b0 Ville Syrjälä     2017-03-27 @3588  	crtc->dspaddr_offset = surf_addr;
4c0b8a8bc Paulo Zanoni      2016-08-19  3589  
282dbf9b0 Ville Syrjälä     2017-03-27  3590  	crtc->adjusted_x = src_x;
282dbf9b0 Ville Syrjälä     2017-03-27  3591  	crtc->adjusted_y = src_y;
2db3366b1 Paulo Zanoni      2015-09-14  3592  
dd584fc07 Ville Syrjälä     2017-03-09  3593  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
dd584fc07 Ville Syrjälä     2017-03-09  3594  
6602be0e2 Rodrigo Vivi      2017-07-06  3595  	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
dd584fc07 Ville Syrjälä     2017-03-09  3596  		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
78587de29 Ville Syrjälä     2017-03-09  3597  			      PLANE_COLOR_PIPE_GAMMA_ENABLE |
78587de29 Ville Syrjälä     2017-03-09  3598  			      PLANE_COLOR_PIPE_CSC_ENABLE |
78587de29 Ville Syrjälä     2017-03-09  3599  			      PLANE_COLOR_PLANE_GAMMA_DISABLE);
78587de29 Ville Syrjälä     2017-03-09  3600  	}
78587de29 Ville Syrjälä     2017-03-09  3601  
dd584fc07 Ville Syrjälä     2017-03-09  3602  	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
dd584fc07 Ville Syrjälä     2017-03-09  3603  	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
dd584fc07 Ville Syrjälä     2017-03-09  3604  	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
dd584fc07 Ville Syrjälä     2017-03-09  3605  	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
2e2adb057 Ville Syrjälä     2017-08-01  3606  	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
2e2adb057 Ville Syrjälä     2017-08-01  3607  		      (plane_state->aux.offset - surf_addr) | aux_stride);
2e2adb057 Ville Syrjälä     2017-08-01  3608  	I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
2e2adb057 Ville Syrjälä     2017-08-01  3609  		      (plane_state->aux.y << 16) | plane_state->aux.x);
6156a4560 Chandra Konduru   2015-04-27  3610  
6156a4560 Chandra Konduru   2015-04-27  3611  	if (scaler_id >= 0) {
6156a4560 Chandra Konduru   2015-04-27  3612  		uint32_t ps_ctrl = 0;
6156a4560 Chandra Konduru   2015-04-27  3613  
6156a4560 Chandra Konduru   2015-04-27  3614  		WARN_ON(!dst_w || !dst_h);
8e816bb49 Ville Syrjälä     2016-11-22  3615  		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
6156a4560 Chandra Konduru   2015-04-27  3616  			crtc_state->scaler_state.scalers[scaler_id].mode;
dd584fc07 Ville Syrjälä     2017-03-09  3617  		I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
dd584fc07 Ville Syrjälä     2017-03-09  3618  		I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
dd584fc07 Ville Syrjälä     2017-03-09  3619  		I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
dd584fc07 Ville Syrjälä     2017-03-09  3620  		I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
dd584fc07 Ville Syrjälä     2017-03-09  3621  		I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
6156a4560 Chandra Konduru   2015-04-27  3622  	} else {
dd584fc07 Ville Syrjälä     2017-03-09  3623  		I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
6156a4560 Chandra Konduru   2015-04-27  3624  	}
6156a4560 Chandra Konduru   2015-04-27  3625  
dd584fc07 Ville Syrjälä     2017-03-09  3626  	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
be1e34151 Chris Wilson      2017-01-16  3627  		      intel_plane_ggtt_offset(plane_state) + surf_addr);
70d21f0e9 Damien Lespiau    2013-07-03  3628  
dd584fc07 Ville Syrjälä     2017-03-09  3629  	POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
dd584fc07 Ville Syrjälä     2017-03-09  3630  
dd584fc07 Ville Syrjälä     2017-03-09  3631  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
70d21f0e9 Damien Lespiau    2013-07-03  3632  }
70d21f0e9 Damien Lespiau    2013-07-03  3633  

:::::: The code at line 3588 was first introduced by commit
:::::: 282dbf9b017bc6d5fdaeadf14e534c2fe22fee2d drm/i915: Pass intel_plane and intel_crtc to plane hooks

:::::: TO: Ville Syrjälä <ville.syrjala@linux.intel.com>
:::::: CC: Ville Syrjälä <ville.syrjala@linux.intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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Re: [PATCH 1/3] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Ville Syrjälä]

On Tue, Sep 12, 2017 at 12:19:38PM +0300, Juha-Pekka Heikkila wrote:
> Move u32 dspaddr_offset from struct intel_crtc member into local
> variable in i9xx_update_primary_plane()

You fail to update the skl function, so this won't build. Please make
sure each step in the series builds (and ideally also works). That way
people can actually bisect through the series.

> 
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
>  drivers/gpu/drm/i915/intel_drv.h     |  1 -
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0871807..0dd0e2a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3307,13 +3307,14 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
>  	int x = plane_state->main.x;
>  	int y = plane_state->main.y;
>  	unsigned long irqflags;
> +	u32 dspaddr_offset;
>  
>  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>  
>  	if (INTEL_GEN(dev_priv) >= 4)
> -		crtc->dspaddr_offset = plane_state->main.offset;
> +		dspaddr_offset = plane_state->main.offset;
>  	else
> -		crtc->dspaddr_offset = linear_offset;
> +		dspaddr_offset = linear_offset;
>  
>  	crtc->adjusted_x = x;
>  	crtc->adjusted_y = y;
> @@ -3342,18 +3343,18 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>  		I915_WRITE_FW(DSPSURF(plane),
>  			      intel_plane_ggtt_offset(plane_state) +
> -			      crtc->dspaddr_offset);
> +			      dspaddr_offset);
>  		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
>  	} else if (INTEL_GEN(dev_priv) >= 4) {
>  		I915_WRITE_FW(DSPSURF(plane),
>  			      intel_plane_ggtt_offset(plane_state) +
> -			      crtc->dspaddr_offset);
> +			      dspaddr_offset);
>  		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
>  		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
>  	} else {
>  		I915_WRITE_FW(DSPADDR(plane),
>  			      intel_plane_ggtt_offset(plane_state) +
> -			      crtc->dspaddr_offset);
> +			      dspaddr_offset);
>  	}
>  	POSTING_READ_FW(reg);
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3078076..d58cd10 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -806,7 +806,6 @@ struct intel_crtc {
>  	/* Display surface base address adjustement for pageflips. Note that on
>  	 * gen4+ this only adjusts up to a tile, offsets within a tile are
>  	 * handled in the hw itself (with the TILEOFF register). */
> -	u32 dspaddr_offset;
>  	int adjusted_x;
>  	int adjusted_y;
>  
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH 1/3] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Juha-Pekka Heikkila]

Move u32 dspaddr_offset from struct intel_crtc member into local
variable in i9xx_update_primary_plane()

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
 drivers/gpu/drm/i915/intel_drv.h     |  1 -
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0871807..0dd0e2a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3307,13 +3307,14 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	int x = plane_state->main.x;
 	int y = plane_state->main.y;
 	unsigned long irqflags;
+	u32 dspaddr_offset;
 
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (INTEL_GEN(dev_priv) >= 4)
-		crtc->dspaddr_offset = plane_state->main.offset;
+		dspaddr_offset = plane_state->main.offset;
 	else
-		crtc->dspaddr_offset = linear_offset;
+		dspaddr_offset = linear_offset;
 
 	crtc->adjusted_x = x;
 	crtc->adjusted_y = y;
@@ -3342,18 +3343,18 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
 		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
 	} else {
 		I915_WRITE_FW(DSPADDR(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 	}
 	POSTING_READ_FW(reg);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3078076..d58cd10 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -806,7 +806,6 @@ struct intel_crtc {
 	/* Display surface base address adjustement for pageflips. Note that on
 	 * gen4+ this only adjusts up to a tile, offsets within a tile are
 	 * handled in the hw itself (with the TILEOFF register). */
-	u32 dspaddr_offset;
 	int adjusted_x;
 	int adjusted_y;
 
-- 
2.7.4

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[PATCH 1/3] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Juha-Pekka Heikkila]

Move u32 dspaddr_offset from struct intel_crtc member into local
variable in i9xx_update_primary_plane()

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
 drivers/gpu/drm/i915/intel_drv.h     |  1 -
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7cd392f..f922e2f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3287,13 +3287,14 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	int x = plane_state->main.x;
 	int y = plane_state->main.y;
 	unsigned long irqflags;
+	u32 dspaddr_offset;
 
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (INTEL_GEN(dev_priv) >= 4)
-		crtc->dspaddr_offset = plane_state->main.offset;
+		dspaddr_offset = plane_state->main.offset;
 	else
-		crtc->dspaddr_offset = linear_offset;
+		dspaddr_offset = linear_offset;
 
 	crtc->adjusted_x = x;
 	crtc->adjusted_y = y;
@@ -3322,18 +3323,18 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
 		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
 	} else {
 		I915_WRITE_FW(DSPADDR(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 	}
 	POSTING_READ_FW(reg);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 17649f1..0d0abed1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -805,7 +805,6 @@ struct intel_crtc {
 	/* Display surface base address adjustement for pageflips. Note that on
 	 * gen4+ this only adjusts up to a tile, offsets within a tile are
 	 * handled in the hw itself (with the TILEOFF register). */
-	u32 dspaddr_offset;
 	int adjusted_x;
 	int adjusted_y;
 
-- 
2.7.4

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[PATCH 1/3] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Juha-Pekka Heikkila]

Move u32 dspaddr_offset from struct intel_crtc member into local
variable in i9xx_update_primary_plane()

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
 drivers/gpu/drm/i915/intel_drv.h     |  1 -
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7cd392f..f922e2f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3287,13 +3287,14 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	int x = plane_state->main.x;
 	int y = plane_state->main.y;
 	unsigned long irqflags;
+	u32 dspaddr_offset;
 
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (INTEL_GEN(dev_priv) >= 4)
-		crtc->dspaddr_offset = plane_state->main.offset;
+		dspaddr_offset = plane_state->main.offset;
 	else
-		crtc->dspaddr_offset = linear_offset;
+		dspaddr_offset = linear_offset;
 
 	crtc->adjusted_x = x;
 	crtc->adjusted_y = y;
@@ -3322,18 +3323,18 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
 		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
 	} else {
 		I915_WRITE_FW(DSPADDR(plane),
 			      intel_plane_ggtt_offset(plane_state) +
-			      crtc->dspaddr_offset);
+			      dspaddr_offset);
 	}
 	POSTING_READ_FW(reg);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 17649f1..0d0abed1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -805,7 +805,6 @@ struct intel_crtc {
 	/* Display surface base address adjustement for pageflips. Note that on
 	 * gen4+ this only adjusts up to a tile, offsets within a tile are
 	 * handled in the hw itself (with the TILEOFF register). */
-	u32 dspaddr_offset;
 	int adjusted_x;
 	int adjusted_y;
 
-- 
2.7.4

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