From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rasesh Mody Subject: [PATCH 09/53] net/qede/base: restrict cache line size register padding Date: Mon, 18 Sep 2017 18:29:49 -0700 Message-ID: <1505784633-1171-10-git-send-email-rasesh.mody@cavium.com> References: <1505784633-1171-1-git-send-email-rasesh.mody@cavium.com> Mime-Version: 1.0 Content-Type: text/plain Cc: Rasesh Mody , Dept-EngDPDKDev@cavium.com To: dev@dpdk.org, ferruh.yigit@intel.com Return-path: Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02on0061.outbound.protection.outlook.com [104.47.37.61]) by dpdk.org (Postfix) with ESMTP id 67DF11B027 for ; Tue, 19 Sep 2017 03:31:15 +0200 (CEST) In-Reply-To: <1505784633-1171-1-git-send-email-rasesh.mody@cavium.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add a restriction on the pad to cache line size register. Signed-off-by: Rasesh Mody --- drivers/net/qede/base/bcm_osal.h | 1 + drivers/net/qede/base/ecore_dev.c | 60 +++++++++++++++++++++++++++++++++++++ drivers/net/qede/base/reg_addr.h | 3 ++ 3 files changed, 64 insertions(+) diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index 6148982..bd07724 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -414,6 +414,7 @@ void qede_hw_err_notify(struct ecore_hwfn *p_hwfn, #define OSAL_REG_ADDR(_p_hwfn, _offset) \ (void *)((u8 *)(uintptr_t)(_p_hwfn->regview) + (_offset)) #define OSAL_PAGE_SIZE 4096 +#define OSAL_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE #define OSAL_IOMEM volatile #define OSAL_UNLIKELY(x) __builtin_expect(!!(x), 0) #define OSAL_MIN_T(type, __min1, __min2) \ diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index 40b544b..73949e8 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -1258,6 +1258,61 @@ static void ecore_init_cau_rt_data(struct ecore_dev *p_dev) } } +static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt) +{ + u32 val, wr_mbs, cache_line_size; + + val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); + switch (val) { + case 0: + wr_mbs = 128; + break; + case 1: + wr_mbs = 256; + break; + case 2: + wr_mbs = 512; + break; + default: + DP_INFO(p_hwfn, + "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", + val); + return; + } + + cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs); + switch (cache_line_size) { + case 32: + val = 0; + break; + case 64: + val = 1; + break; + case 128: + val = 2; + break; + case 256: + val = 3; + break; + default: + DP_INFO(p_hwfn, + "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", + cache_line_size); + } + + if (wr_mbs < OSAL_CACHE_LINE_SIZE) + DP_INFO(p_hwfn, + "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", + OSAL_CACHE_LINE_SIZE, wr_mbs); + + STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); + if (val > 0) { + STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); + STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); + } +} + static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, int hw_mode) @@ -1298,6 +1353,8 @@ static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn, ecore_cxt_hw_init_common(p_hwfn); + ecore_init_cache_line_size(p_hwfn, p_ptt); + rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); if (rc != ECORE_SUCCESS) return rc; @@ -1686,6 +1743,9 @@ static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn, hw_mode); if (rc != ECORE_SUCCESS) return rc; + + ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); + #ifndef ASIC_ONLY if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) return ECORE_SUCCESS; diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h index 6028654..116fe78 100644 --- a/drivers/net/qede/base/reg_addr.h +++ b/drivers/net/qede/base/reg_addr.h @@ -1205,3 +1205,6 @@ #define NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 0x501a80UL #define NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 0x501ac0UL #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 0x501b00UL + +#define PSWRQ2_REG_WR_MBS0 0x240400UL +#define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL -- 1.7.10.3