From: Rasesh Mody <rasesh.mody@cavium.com>
To: dev@dpdk.org, ferruh.yigit@intel.com
Cc: Rasesh Mody <rasesh.mody@cavium.com>, Dept-EngDPDKDev@cavium.com
Subject: [PATCH 22/53] net/qede/base: rename MFW get/set field defines
Date: Mon, 18 Sep 2017 18:30:02 -0700 [thread overview]
Message-ID: <1505784633-1171-23-git-send-email-rasesh.mody@cavium.com> (raw)
In-Reply-To: <1505784633-1171-1-git-send-email-rasesh.mody@cavium.com>
Changes for management FW, change of _SHIFT defines to _OFFSET.
Accordingly, rename and fix the ECORE_MFW_GET_FIELD() and
ECORE_MFW_SET_FIELD() macros and update wherever used.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/qede/base/ecore.h | 12 +-
drivers/net/qede/base/ecore_dcbx.c | 125 +++++++++---------
drivers/net/qede/base/ecore_dev.c | 2 +-
drivers/net/qede/base/ecore_mcp.c | 166 ++++++++++++------------
drivers/net/qede/base/mcp_public.h | 252 ++++++++++++++++++------------------
5 files changed, 273 insertions(+), 284 deletions(-)
diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h
index 818a34b..71f27da 100644
--- a/drivers/net/qede/base/ecore.h
+++ b/drivers/net/qede/base/ecore.h
@@ -98,16 +98,16 @@ enum ecore_nvm_cmd {
#define GET_FIELD(value, name) \
(((value) >> (name##_SHIFT)) & name##_MASK)
-#endif
-#define ECORE_MFW_GET_FIELD(name, field) \
- (((name) & (field ## _MASK)) >> (field ## _SHIFT))
+#define GET_MFW_FIELD(name, field) \
+ (((name) & (field ## _MASK)) >> (field ## _OFFSET))
-#define ECORE_MFW_SET_FIELD(name, field, value) \
+#define SET_MFW_FIELD(name, field, value) \
do { \
- (name) &= ~(field ## _MASK); \
- (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK)); \
+ (name) &= ~((field ## _MASK)); \
+ (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
} while (0)
+#endif
static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
{
diff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c
index 4f1b069..cce2830 100644
--- a/drivers/net/qede/base/ecore_dcbx.c
+++ b/drivers/net/qede/base/ecore_dcbx.c
@@ -28,13 +28,13 @@
static bool ecore_dcbx_app_ethtype(u32 app_info_bitmap)
{
- return !!(ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF) ==
+ return !!(GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF) ==
DCBX_APP_SF_ETHTYPE);
}
static bool ecore_dcbx_ieee_app_ethtype(u32 app_info_bitmap)
{
- u8 mfw_val = ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE);
+ u8 mfw_val = GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE);
/* Old MFW */
if (mfw_val == DCBX_APP_SF_IEEE_RESERVED)
@@ -45,13 +45,13 @@ static bool ecore_dcbx_ieee_app_ethtype(u32 app_info_bitmap)
static bool ecore_dcbx_app_port(u32 app_info_bitmap)
{
- return !!(ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF) ==
+ return !!(GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF) ==
DCBX_APP_SF_PORT);
}
static bool ecore_dcbx_ieee_app_port(u32 app_info_bitmap, u8 type)
{
- u8 mfw_val = ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE);
+ u8 mfw_val = GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE);
/* Old MFW */
if (mfw_val == DCBX_APP_SF_IEEE_RESERVED)
@@ -248,10 +248,9 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
ieee = (dcbx_version == DCBX_CONFIG_VERSION_IEEE);
/* Parse APP TLV */
for (i = 0; i < count; i++) {
- protocol_id = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
- DCBX_APP_PROTOCOL_ID);
- priority_map = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
- DCBX_APP_PRI_MAP);
+ protocol_id = GET_MFW_FIELD(p_tbl[i].entry,
+ DCBX_APP_PROTOCOL_ID);
+ priority_map = GET_MFW_FIELD(p_tbl[i].entry, DCBX_APP_PRI_MAP);
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Id = 0x%x pri_map = %u\n",
protocol_id, priority_map);
rc = ecore_dcbx_get_app_priority(priority_map, &priority);
@@ -313,7 +312,7 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
int num_entries;
flags = p_hwfn->p_dcbx_info->operational.flags;
- dcbx_version = ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION);
+ dcbx_version = GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION);
p_app = &p_hwfn->p_dcbx_info->operational.features.app;
p_tbl = p_app->app_pri_tbl;
@@ -322,16 +321,15 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
pri_tc_tbl = p_ets->pri_tc_tbl[0];
p_info = &p_hwfn->hw_info;
- num_entries = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_NUM_ENTRIES);
+ num_entries = GET_MFW_FIELD(p_app->flags, DCBX_APP_NUM_ENTRIES);
rc = ecore_dcbx_process_tlv(p_hwfn, &data, p_tbl, pri_tc_tbl,
num_entries, dcbx_version);
if (rc != ECORE_SUCCESS)
return rc;
- p_info->num_active_tc = ECORE_MFW_GET_FIELD(p_ets->flags,
- DCBX_ETS_MAX_TCS);
- p_hwfn->qm_info.ooo_tc = ECORE_MFW_GET_FIELD(p_ets->flags, DCBX_OOO_TC);
+ p_info->num_active_tc = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_MAX_TCS);
+ p_hwfn->qm_info.ooo_tc = GET_MFW_FIELD(p_ets->flags, DCBX_OOO_TC);
data.pf_id = p_hwfn->rel_pf_id;
data.dcbx_enabled = !!dcbx_version;
@@ -414,26 +412,24 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
u8 pri_map;
int i;
- p_params->app_willing = ECORE_MFW_GET_FIELD(p_app->flags,
- DCBX_APP_WILLING);
- p_params->app_valid = ECORE_MFW_GET_FIELD(p_app->flags,
- DCBX_APP_ENABLED);
- p_params->app_error = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_ERROR);
- p_params->num_app_entries = ECORE_MFW_GET_FIELD(p_app->flags,
- DCBX_APP_NUM_ENTRIES);
+ p_params->app_willing = GET_MFW_FIELD(p_app->flags, DCBX_APP_WILLING);
+ p_params->app_valid = GET_MFW_FIELD(p_app->flags, DCBX_APP_ENABLED);
+ p_params->app_error = GET_MFW_FIELD(p_app->flags, DCBX_APP_ERROR);
+ p_params->num_app_entries = GET_MFW_FIELD(p_app->flags,
+ DCBX_APP_NUM_ENTRIES);
for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
entry = &p_params->app_entry[i];
if (ieee) {
u8 sf_ieee;
u32 val;
- sf_ieee = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
- DCBX_APP_SF_IEEE);
+ sf_ieee = GET_MFW_FIELD(p_tbl[i].entry,
+ DCBX_APP_SF_IEEE);
switch (sf_ieee) {
case DCBX_APP_SF_IEEE_RESERVED:
/* Old MFW */
- val = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
- DCBX_APP_SF);
+ val = GET_MFW_FIELD(p_tbl[i].entry,
+ DCBX_APP_SF);
entry->sf_ieee = val ?
ECORE_DCBX_SF_IEEE_TCP_UDP_PORT :
ECORE_DCBX_SF_IEEE_ETHTYPE;
@@ -453,14 +449,14 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
break;
}
} else {
- entry->ethtype = !(ECORE_MFW_GET_FIELD(p_tbl[i].entry,
- DCBX_APP_SF));
+ entry->ethtype = !(GET_MFW_FIELD(p_tbl[i].entry,
+ DCBX_APP_SF));
}
- pri_map = ECORE_MFW_GET_FIELD(p_tbl[i].entry, DCBX_APP_PRI_MAP);
+ pri_map = GET_MFW_FIELD(p_tbl[i].entry, DCBX_APP_PRI_MAP);
ecore_dcbx_get_app_priority(pri_map, &entry->prio);
- entry->proto_id = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
- DCBX_APP_PROTOCOL_ID);
+ entry->proto_id = GET_MFW_FIELD(p_tbl[i].entry,
+ DCBX_APP_PROTOCOL_ID);
ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry,
entry->proto_id,
&entry->proto_type, ieee);
@@ -478,10 +474,10 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
{
u8 pfc_map;
- p_params->pfc.willing = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_WILLING);
- p_params->pfc.max_tc = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_CAPS);
- p_params->pfc.enabled = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_ENABLED);
- pfc_map = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_PRI_EN_BITMAP);
+ p_params->pfc.willing = GET_MFW_FIELD(pfc, DCBX_PFC_WILLING);
+ p_params->pfc.max_tc = GET_MFW_FIELD(pfc, DCBX_PFC_CAPS);
+ p_params->pfc.enabled = GET_MFW_FIELD(pfc, DCBX_PFC_ENABLED);
+ pfc_map = GET_MFW_FIELD(pfc, DCBX_PFC_PRI_EN_BITMAP);
p_params->pfc.prio[0] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_0);
p_params->pfc.prio[1] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_1);
p_params->pfc.prio[2] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_2);
@@ -505,13 +501,10 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
u32 bw_map[2], tsa_map[2], pri_map;
int i;
- p_params->ets_willing = ECORE_MFW_GET_FIELD(p_ets->flags,
- DCBX_ETS_WILLING);
- p_params->ets_enabled = ECORE_MFW_GET_FIELD(p_ets->flags,
- DCBX_ETS_ENABLED);
- p_params->ets_cbs = ECORE_MFW_GET_FIELD(p_ets->flags, DCBX_ETS_CBS);
- p_params->max_ets_tc = ECORE_MFW_GET_FIELD(p_ets->flags,
- DCBX_ETS_MAX_TCS);
+ p_params->ets_willing = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_WILLING);
+ p_params->ets_enabled = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_ENABLED);
+ p_params->ets_cbs = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_CBS);
+ p_params->max_ets_tc = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_MAX_TCS);
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
"ETS params: willing %d, enabled = %d ets_cbs %d pri_tc_tbl_0 %x max_ets_tc %d\n",
p_params->ets_willing, p_params->ets_enabled,
@@ -597,7 +590,7 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
* was successfuly performed
*/
p_operational = ¶ms->operational;
- enabled = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) !=
+ enabled = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) !=
DCBX_CONFIG_VERSION_DISABLED);
if (!enabled) {
p_operational->enabled = enabled;
@@ -609,15 +602,15 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
p_feat = &p_hwfn->p_dcbx_info->operational.features;
p_results = &p_hwfn->p_dcbx_info->results;
- val = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) ==
+ val = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) ==
DCBX_CONFIG_VERSION_IEEE);
p_operational->ieee = val;
- val = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) ==
+ val = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) ==
DCBX_CONFIG_VERSION_CEE);
p_operational->cee = val;
- val = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) ==
+ val = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) ==
DCBX_CONFIG_VERSION_STATIC);
p_operational->local = val;
@@ -632,7 +625,7 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
p_operational->ieee);
ecore_dcbx_get_priority_info(p_hwfn, &p_operational->app_prio,
p_results);
- err = ECORE_MFW_GET_FIELD(p_feat->app.flags, DCBX_APP_ERROR);
+ err = GET_MFW_FIELD(p_feat->app.flags, DCBX_APP_ERROR);
p_operational->err = err;
p_operational->enabled = enabled;
p_operational->valid = true;
@@ -652,8 +645,8 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
p_dscp = ¶ms->dscp;
p_dscp_map = &p_hwfn->p_dcbx_info->dscp_map;
- p_dscp->enabled = ECORE_MFW_GET_FIELD(p_dscp_map->flags,
- DCB_DSCP_ENABLE);
+ p_dscp->enabled = GET_MFW_FIELD(p_dscp_map->flags, DCB_DSCP_ENABLE);
+
/* MFW encodes 64 dscp entries into 8 element array of u32 entries,
* where each entry holds the 4bit priority map for 8 dscp entries.
*/
@@ -1010,13 +1003,13 @@ enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn,
*pfc &= ~DCBX_PFC_ENABLED_MASK;
*pfc &= ~DCBX_PFC_CAPS_MASK;
- *pfc |= (u32)p_params->pfc.max_tc << DCBX_PFC_CAPS_SHIFT;
+ *pfc |= (u32)p_params->pfc.max_tc << DCBX_PFC_CAPS_OFFSET;
for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++)
if (p_params->pfc.prio[i])
pfc_map |= (1 << i);
*pfc &= ~DCBX_PFC_PRI_EN_BITMAP_MASK;
- *pfc |= (pfc_map << DCBX_PFC_PRI_EN_BITMAP_SHIFT);
+ *pfc |= (pfc_map << DCBX_PFC_PRI_EN_BITMAP_OFFSET);
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "pfc = 0x%x\n", *pfc);
}
@@ -1046,7 +1039,7 @@ enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn,
p_ets->flags &= ~DCBX_ETS_ENABLED_MASK;
p_ets->flags &= ~DCBX_ETS_MAX_TCS_MASK;
- p_ets->flags |= (u32)p_params->max_ets_tc << DCBX_ETS_MAX_TCS_SHIFT;
+ p_ets->flags |= (u32)p_params->max_ets_tc << DCBX_ETS_MAX_TCS_OFFSET;
bw_map = (u8 *)&p_ets->tc_bw_tbl[0];
tsa_map = (u8 *)&p_ets->tc_tsa_tbl[0];
@@ -1092,7 +1085,7 @@ enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn,
p_app->flags &= ~DCBX_APP_NUM_ENTRIES_MASK;
p_app->flags |= (u32)p_params->num_app_entries <<
- DCBX_APP_NUM_ENTRIES_SHIFT;
+ DCBX_APP_NUM_ENTRIES_OFFSET;
for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
entry = &p_app->app_pri_tbl[i].entry;
@@ -1102,44 +1095,44 @@ enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn,
switch (p_params->app_entry[i].sf_ieee) {
case ECORE_DCBX_SF_IEEE_ETHTYPE:
*entry |= ((u32)DCBX_APP_SF_IEEE_ETHTYPE <<
- DCBX_APP_SF_IEEE_SHIFT);
+ DCBX_APP_SF_IEEE_OFFSET);
*entry |= ((u32)DCBX_APP_SF_ETHTYPE <<
- DCBX_APP_SF_SHIFT);
+ DCBX_APP_SF_OFFSET);
break;
case ECORE_DCBX_SF_IEEE_TCP_PORT:
*entry |= ((u32)DCBX_APP_SF_IEEE_TCP_PORT <<
- DCBX_APP_SF_IEEE_SHIFT);
+ DCBX_APP_SF_IEEE_OFFSET);
*entry |= ((u32)DCBX_APP_SF_PORT <<
- DCBX_APP_SF_SHIFT);
+ DCBX_APP_SF_OFFSET);
break;
case ECORE_DCBX_SF_IEEE_UDP_PORT:
*entry |= ((u32)DCBX_APP_SF_IEEE_UDP_PORT <<
- DCBX_APP_SF_IEEE_SHIFT);
+ DCBX_APP_SF_IEEE_OFFSET);
*entry |= ((u32)DCBX_APP_SF_PORT <<
- DCBX_APP_SF_SHIFT);
+ DCBX_APP_SF_OFFSET);
break;
case ECORE_DCBX_SF_IEEE_TCP_UDP_PORT:
*entry |= (u32)DCBX_APP_SF_IEEE_TCP_UDP_PORT <<
- DCBX_APP_SF_IEEE_SHIFT;
+ DCBX_APP_SF_IEEE_OFFSET;
*entry |= ((u32)DCBX_APP_SF_PORT <<
- DCBX_APP_SF_SHIFT);
+ DCBX_APP_SF_OFFSET);
break;
}
} else {
*entry &= ~DCBX_APP_SF_MASK;
if (p_params->app_entry[i].ethtype)
*entry |= ((u32)DCBX_APP_SF_ETHTYPE <<
- DCBX_APP_SF_SHIFT);
+ DCBX_APP_SF_OFFSET);
else
*entry |= ((u32)DCBX_APP_SF_PORT <<
- DCBX_APP_SF_SHIFT);
+ DCBX_APP_SF_OFFSET);
}
*entry &= ~DCBX_APP_PROTOCOL_ID_MASK;
*entry |= ((u32)p_params->app_entry[i].proto_id <<
- DCBX_APP_PROTOCOL_ID_SHIFT);
+ DCBX_APP_PROTOCOL_ID_OFFSET);
*entry &= ~DCBX_APP_PRI_MAP_MASK;
*entry |= ((u32)(p_params->app_entry[i].prio) <<
- DCBX_APP_PRI_MAP_SHIFT);
+ DCBX_APP_PRI_MAP_OFFSET);
}
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "flags = 0x%x\n", p_app->flags);
@@ -1253,12 +1246,10 @@ enum _ecore_status_t ecore_dcbx_config_params(struct ecore_hwfn *p_hwfn,
}
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_DCBX,
- 1 << DRV_MB_PARAM_LLDP_SEND_SHIFT, &resp, ¶m);
- if (rc != ECORE_SUCCESS) {
+ 1 << DRV_MB_PARAM_LLDP_SEND_OFFSET, &resp, ¶m);
+ if (rc != ECORE_SUCCESS)
DP_NOTICE(p_hwfn, false,
"Failed to send DCBX update request\n");
- return rc;
- }
return rc;
}
diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 40959e7..2fe30d7 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -2159,7 +2159,7 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
"sending phony dcbx set command to trigger DCBx attention handling\n");
rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
DRV_MSG_CODE_SET_DCBX,
- 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, &resp,
+ 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
¶m);
if (rc != ECORE_SUCCESS) {
DP_NOTICE(p_hwfn, true,
diff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c
index 7169b55..0f96c91 100644
--- a/drivers/net/qede/base/ecore_mcp.c
+++ b/drivers/net/qede/base/ecore_mcp.c
@@ -43,9 +43,9 @@
OFFSETOF(struct public_drv_mb, _field))
#define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
- DRV_ID_PDA_COMP_VER_SHIFT)
+ DRV_ID_PDA_COMP_VER_OFFSET)
-#define MCP_BYTES_PER_MBIT_SHIFT 17
+#define MCP_BYTES_PER_MBIT_OFFSET 17
#ifndef ASIC_ONLY
static int loaded;
@@ -804,18 +804,16 @@ struct ecore_load_req_out_params {
load_req.drv_ver_0 = p_in_params->drv_ver_0;
load_req.drv_ver_1 = p_in_params->drv_ver_1;
load_req.fw_ver = p_in_params->fw_ver;
- ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE,
- p_in_params->drv_role);
- ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
- p_in_params->timeout_val);
- ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
- p_in_params->force_cmd);
- ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
- p_in_params->avoid_eng_reset);
+ SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
+ SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
+ p_in_params->timeout_val);
+ SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
+ SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
+ p_in_params->avoid_eng_reset);
hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
DRV_ID_MCP_HSI_VER_CURRENT :
- (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
+ (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
@@ -828,22 +826,20 @@ struct ecore_load_req_out_params {
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
mb_params.param,
- ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
- ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
- ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
- ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
+ GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
+ GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
+ GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
+ GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
load_req.drv_ver_0, load_req.drv_ver_1,
load_req.fw_ver, load_req.misc0,
- ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
- ECORE_MFW_GET_FIELD(load_req.misc0,
- LOAD_REQ_LOCK_TO),
- ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
- ECORE_MFW_GET_FIELD(load_req.misc0,
- LOAD_REQ_FLAGS0));
+ GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
+ GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
+ GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
+ GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
if (rc != ECORE_SUCCESS) {
@@ -862,20 +858,19 @@ struct ecore_load_req_out_params {
"Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
load_rsp.drv_ver_0, load_rsp.drv_ver_1,
load_rsp.fw_ver, load_rsp.misc0,
- ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
- ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
- ECORE_MFW_GET_FIELD(load_rsp.misc0,
- LOAD_RSP_FLAGS0));
+ GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
+ GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
+ GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
p_out_params->exist_fw_ver = load_rsp.fw_ver;
p_out_params->exist_drv_role =
- ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
+ GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
p_out_params->mfw_hsi_ver =
- ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
+ GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
p_out_params->drv_exists =
- ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
+ GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
LOAD_RSP_FLAGS0_DRV_EXISTS;
}
@@ -1174,7 +1169,8 @@ static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
OFFSETOF(struct public_port,
transceiver_data)));
- transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
+ transceiver_state = GET_MFW_FIELD(transceiver_state,
+ ETH_TRANSCEIVER_STATE);
if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
@@ -1193,12 +1189,12 @@ static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
OFFSETOF(struct public_port, eee_status));
p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
- val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_SHIFT;
+ val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
if (val & EEE_1G_ADV)
p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
if (val & EEE_10G_ADV)
p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
- val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_SHIFT;
+ val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
if (val & EEE_1G_ADV)
p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
if (val & EEE_10G_ADV)
@@ -1391,7 +1387,7 @@ enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
- EEE_TX_TIMER_USEC_SHIFT) &
+ EEE_TX_TIMER_USEC_OFFSET) &
EEE_TX_TIMER_USEC_MASK;
}
@@ -1531,7 +1527,7 @@ static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
*/
p_info->bandwidth_min = (p_shmem_info->config &
FUNC_MF_CFG_MIN_BW_MASK) >>
- FUNC_MF_CFG_MIN_BW_SHIFT;
+ FUNC_MF_CFG_MIN_BW_OFFSET;
if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
DP_INFO(p_hwfn,
"bandwidth minimum out of bounds [%02x]. Set to 1\n",
@@ -1541,7 +1537,7 @@ static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
p_info->bandwidth_max = (p_shmem_info->config &
FUNC_MF_CFG_MAX_BW_MASK) >>
- FUNC_MF_CFG_MAX_BW_SHIFT;
+ FUNC_MF_CFG_MAX_BW_OFFSET;
if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
DP_INFO(p_hwfn,
"bandwidth maximum out of bounds [%02x]. Set to 100\n",
@@ -2226,8 +2222,8 @@ enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
- MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
- flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
+ MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
+ flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
*p_flash_size = flash_size;
@@ -2265,9 +2261,9 @@ enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
return ECORE_SUCCESS;
num *= p_hwfn->p_dev->num_hwfns;
- param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
+ param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
- param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
+ param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
@@ -2501,7 +2497,7 @@ enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
MCP_DRV_NVM_BUF_LEN);
nvm_offset = (addr + offset) | (bytes_to_copy <<
- DRV_MB_PARAM_NVM_LEN_SHIFT);
+ DRV_MB_PARAM_NVM_LEN_OFFSET);
rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
DRV_MSG_CODE_NVM_READ_NVRAM,
nvm_offset, &resp, ¶m, &buf_size,
@@ -2652,8 +2648,9 @@ enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
while (buf_idx < len) {
buf_size = OSAL_MIN_T(u32, (len - buf_idx),
MCP_DRV_NVM_BUF_LEN);
- nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_SHIFT) | addr) +
- buf_idx;
+ nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
+ addr) +
+ buf_idx;
rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
&resp, ¶m, buf_size,
(u32 *)&p_buf[buf_idx]);
@@ -2744,8 +2741,8 @@ enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
u32 resp, param;
enum _ecore_status_t rc;
- nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
- (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
+ nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
+ (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
addr = offset;
offset = 0;
bytes_left = len;
@@ -2755,9 +2752,9 @@ enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
nvm_offset |= ((addr + offset) <<
- DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
+ DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
nvm_offset |= (bytes_to_copy <<
- DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
+ DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
DRV_MSG_CODE_TRANSCEIVER_READ,
nvm_offset, &resp, ¶m, &buf_size,
@@ -2784,8 +2781,8 @@ enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
u32 buf_idx, buf_size, nvm_offset, resp, param;
enum _ecore_status_t rc;
- nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
- (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
+ nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
+ (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
buf_idx = 0;
while (buf_idx < len) {
buf_size = OSAL_MIN_T(u32, (len - buf_idx),
@@ -2793,8 +2790,9 @@ enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
nvm_offset |= ((offset + buf_idx) <<
- DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
- nvm_offset |= (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
+ DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
+ nvm_offset |= (buf_size <<
+ DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
DRV_MSG_CODE_TRANSCEIVER_WRITE,
nvm_offset, &resp, ¶m, buf_size,
@@ -2819,7 +2817,7 @@ enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t rc = ECORE_SUCCESS;
u32 drv_mb_param = 0, rsp;
- drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
+ drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
drv_mb_param, &rsp, gpio_val);
@@ -2840,8 +2838,8 @@ enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t rc = ECORE_SUCCESS;
u32 drv_mb_param = 0, param, rsp;
- drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
- (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
+ drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
+ (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
drv_mb_param, &rsp, ¶m);
@@ -2863,7 +2861,7 @@ enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
u32 drv_mb_param = 0, rsp, val = 0;
enum _ecore_status_t rc = ECORE_SUCCESS;
- drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
+ drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
drv_mb_param, &rsp, &val);
@@ -2871,9 +2869,9 @@ enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
return rc;
*gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
- DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
+ DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
*gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
- DRV_MB_PARAM_GPIO_CTRL_SHIFT;
+ DRV_MB_PARAM_GPIO_CTRL_OFFSET;
if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
return ECORE_UNKNOWN_ERROR;
@@ -2888,7 +2886,7 @@ enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t rc = ECORE_SUCCESS;
drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
- DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
+ DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
drv_mb_param, &rsp, ¶m);
@@ -2910,7 +2908,7 @@ enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t rc = ECORE_SUCCESS;
drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
- DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
+ DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
drv_mb_param, &rsp, ¶m);
@@ -2932,7 +2930,7 @@ enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
enum _ecore_status_t rc = ECORE_SUCCESS;
drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
- DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
+ DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
drv_mb_param, &rsp, num_images);
@@ -2954,8 +2952,9 @@ enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
enum _ecore_status_t rc;
nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
- DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
- nvm_offset |= (image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
+ DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
+ nvm_offset |= (image_index <<
+ DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
nvm_offset, &resp, ¶m, &buf_size,
(u32 *)p_image_att);
@@ -2996,13 +2995,13 @@ enum _ecore_status_t
val = mfw_temp_info.sensor[i];
p_temp_sensor = &p_temp_info->sensors[i];
p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
- SENSOR_LOCATION_SHIFT;
+ SENSOR_LOCATION_OFFSET;
p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
- THRESHOLD_HIGH_SHIFT;
+ THRESHOLD_HIGH_OFFSET;
p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
- CRITICAL_TEMPERATURE_SHIFT;
+ CRITICAL_TEMPERATURE_OFFSET;
p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
- CURRENT_TEMP_SHIFT;
+ CURRENT_TEMP_OFFSET;
}
return ECORE_SUCCESS;
@@ -3099,9 +3098,9 @@ enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
#define ECORE_RESC_ALLOC_VERSION_MINOR 0
#define ECORE_RESC_ALLOC_VERSION \
((ECORE_RESC_ALLOC_VERSION_MAJOR << \
- DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
+ DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) | \
(ECORE_RESC_ALLOC_VERSION_MINOR << \
- DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
+ DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
struct ecore_resc_alloc_in_params {
u32 cmd;
@@ -3185,10 +3184,10 @@ enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
"Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
p_in_params->cmd, p_in_params->res_id,
ecore_hw_get_resc_name(p_in_params->res_id),
- ECORE_MFW_GET_FIELD(mb_params.param,
- DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
- ECORE_MFW_GET_FIELD(mb_params.param,
- DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
+ GET_MFW_FIELD(mb_params.param,
+ DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
+ GET_MFW_FIELD(mb_params.param,
+ DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
p_in_params->resc_max_val);
rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
@@ -3205,10 +3204,10 @@ enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
- ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
- FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
- ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
- FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
+ GET_MFW_FIELD(p_out_params->mcp_param,
+ FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
+ GET_MFW_FIELD(p_out_params->mcp_param,
+ FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
p_out_params->resc_num, p_out_params->resc_start,
p_out_params->vf_resc_num, p_out_params->vf_resc_start,
p_out_params->flags);
@@ -3296,7 +3295,7 @@ static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
}
if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
- u8 opcode = ECORE_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
+ u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
DP_NOTICE(p_hwfn, false,
"The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
@@ -3329,9 +3328,9 @@ enum _ecore_status_t
break;
}
- ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
- ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
- ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
+ SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
+ SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
+ SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
@@ -3344,9 +3343,8 @@ enum _ecore_status_t
return rc;
/* Analyze the response */
- p_params->owner = ECORE_MFW_GET_FIELD(mcp_param,
- RESOURCE_CMD_RSP_OWNER);
- opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
+ p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
+ opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
@@ -3443,8 +3441,8 @@ enum _ecore_status_t
opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
: RESOURCE_OPCODE_RELEASE;
- ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
- ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
+ SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
+ SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
@@ -3457,7 +3455,7 @@ enum _ecore_status_t
return rc;
/* Analyze the response */
- opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
+ opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h
index 8484704..ff9ce9e 100644
--- a/drivers/net/qede/base/mcp_public.h
+++ b/drivers/net/qede/base/mcp_public.h
@@ -28,19 +28,19 @@
typedef u32 offsize_t; /* In DWORDS !!! */
/* Offset from the beginning of the MCP scratchpad */
-#define OFFSIZE_OFFSET_SHIFT 0
+#define OFFSIZE_OFFSET_OFFSET 0
#define OFFSIZE_OFFSET_MASK 0x0000ffff
/* Size of specific element (not the whole array if any) */
-#define OFFSIZE_SIZE_SHIFT 16
+#define OFFSIZE_SIZE_OFFSET 16
#define OFFSIZE_SIZE_MASK 0xffff0000
/* SECTION_OFFSET is calculating the offset in bytes out of offsize */
#define SECTION_OFFSET(_offsize) \
- ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2))
+ ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_OFFSET) << 2))
/* SECTION_SIZE is calculating the size in bytes out of offsize */
#define SECTION_SIZE(_offsize) \
- (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2)
+ (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_OFFSET) << 2)
/* SECTION_ADDR returns the GRC addr of a section, given offsize and index
* within section
@@ -93,7 +93,7 @@ struct eth_phy_cfg {
#define EEE_CFG_ADV_SPEED_1G (1 << 2)
#define EEE_CFG_ADV_SPEED_10G (1 << 3)
#define EEE_TX_TIMER_USEC_MASK (0xfffffff0)
-#define EEE_TX_TIMER_USEC_SHIFT 4
+#define EEE_TX_TIMER_USEC_OFFSET 4
#define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00)
#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100)
#define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000)
@@ -105,7 +105,7 @@ struct eth_phy_cfg {
struct port_mf_cfg {
u32 dynamic_cfg; /* device control channel */
#define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
-#define PORT_MF_CFG_OV_TAG_SHIFT 0
+#define PORT_MF_CFG_OV_TAG_OFFSET 0
#define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
u32 reserved[1];
@@ -279,15 +279,15 @@ struct couple_mode_teaming {
struct lldp_config_params_s {
u32 config;
#define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
-#define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
+#define LLDP_CONFIG_TX_INTERVAL_OFFSET 0
#define LLDP_CONFIG_HOLD_MASK 0x00000f00
-#define LLDP_CONFIG_HOLD_SHIFT 8
+#define LLDP_CONFIG_HOLD_OFFSET 8
#define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
-#define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
+#define LLDP_CONFIG_MAX_CREDIT_OFFSET 12
#define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
-#define LLDP_CONFIG_ENABLE_RX_SHIFT 30
+#define LLDP_CONFIG_ENABLE_RX_OFFSET 30
#define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
-#define LLDP_CONFIG_ENABLE_TX_SHIFT 31
+#define LLDP_CONFIG_ENABLE_TX_OFFSET 31
/* Holds local Chassis ID TLV header, subtype and 9B of payload.
* If firtst byte is 0, then we will use default chassis ID
*/
@@ -311,17 +311,17 @@ struct lldp_status_params_s {
struct dcbx_ets_feature {
u32 flags;
#define DCBX_ETS_ENABLED_MASK 0x00000001
-#define DCBX_ETS_ENABLED_SHIFT 0
+#define DCBX_ETS_ENABLED_OFFSET 0
#define DCBX_ETS_WILLING_MASK 0x00000002
-#define DCBX_ETS_WILLING_SHIFT 1
+#define DCBX_ETS_WILLING_OFFSET 1
#define DCBX_ETS_ERROR_MASK 0x00000004
-#define DCBX_ETS_ERROR_SHIFT 2
+#define DCBX_ETS_ERROR_OFFSET 2
#define DCBX_ETS_CBS_MASK 0x00000008
-#define DCBX_ETS_CBS_SHIFT 3
+#define DCBX_ETS_CBS_OFFSET 3
#define DCBX_ETS_MAX_TCS_MASK 0x000000f0
-#define DCBX_ETS_MAX_TCS_SHIFT 4
+#define DCBX_ETS_MAX_TCS_OFFSET 4
#define DCBX_OOO_TC_MASK 0x00000f00
-#define DCBX_OOO_TC_SHIFT 8
+#define DCBX_OOO_TC_OFFSET 8
/* Entries in tc table are orginized that the left most is pri 0, right most is
* prio 7
*/
@@ -353,7 +353,7 @@ struct dcbx_ets_feature {
struct dcbx_app_priority_entry {
u32 entry;
#define DCBX_APP_PRI_MAP_MASK 0x000000ff
-#define DCBX_APP_PRI_MAP_SHIFT 0
+#define DCBX_APP_PRI_MAP_OFFSET 0
#define DCBX_APP_PRI_0 0x01
#define DCBX_APP_PRI_1 0x02
#define DCBX_APP_PRI_2 0x04
@@ -363,11 +363,11 @@ struct dcbx_app_priority_entry {
#define DCBX_APP_PRI_6 0x40
#define DCBX_APP_PRI_7 0x80
#define DCBX_APP_SF_MASK 0x00000300
-#define DCBX_APP_SF_SHIFT 8
+#define DCBX_APP_SF_OFFSET 8
#define DCBX_APP_SF_ETHTYPE 0
#define DCBX_APP_SF_PORT 1
#define DCBX_APP_SF_IEEE_MASK 0x0000f000
-#define DCBX_APP_SF_IEEE_SHIFT 12
+#define DCBX_APP_SF_IEEE_OFFSET 12
#define DCBX_APP_SF_IEEE_RESERVED 0
#define DCBX_APP_SF_IEEE_ETHTYPE 1
#define DCBX_APP_SF_IEEE_TCP_PORT 2
@@ -375,7 +375,7 @@ struct dcbx_app_priority_entry {
#define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
#define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
-#define DCBX_APP_PROTOCOL_ID_SHIFT 16
+#define DCBX_APP_PROTOCOL_ID_OFFSET 16
};
@@ -383,19 +383,19 @@ struct dcbx_app_priority_entry {
struct dcbx_app_priority_feature {
u32 flags;
#define DCBX_APP_ENABLED_MASK 0x00000001
-#define DCBX_APP_ENABLED_SHIFT 0
+#define DCBX_APP_ENABLED_OFFSET 0
#define DCBX_APP_WILLING_MASK 0x00000002
-#define DCBX_APP_WILLING_SHIFT 1
+#define DCBX_APP_WILLING_OFFSET 1
#define DCBX_APP_ERROR_MASK 0x00000004
-#define DCBX_APP_ERROR_SHIFT 2
+#define DCBX_APP_ERROR_OFFSET 2
/* Not in use
#define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
- #define DCBX_APP_DEFAULT_PRI_SHIFT 8
+ #define DCBX_APP_DEFAULT_PRI_OFFSET 8
*/
#define DCBX_APP_MAX_TCS_MASK 0x0000f000
-#define DCBX_APP_MAX_TCS_SHIFT 12
+#define DCBX_APP_MAX_TCS_OFFSET 12
#define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
-#define DCBX_APP_NUM_ENTRIES_SHIFT 16
+#define DCBX_APP_NUM_ENTRIES_OFFSET 16
struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
};
@@ -406,7 +406,7 @@ struct dcbx_features {
/* PFC feature */
u32 pfc;
#define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
-#define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
+#define DCBX_PFC_PRI_EN_BITMAP_OFFSET 0
#define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
#define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
#define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
@@ -417,17 +417,17 @@ struct dcbx_features {
#define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
#define DCBX_PFC_FLAGS_MASK 0x0000ff00
-#define DCBX_PFC_FLAGS_SHIFT 8
+#define DCBX_PFC_FLAGS_OFFSET 8
#define DCBX_PFC_CAPS_MASK 0x00000f00
-#define DCBX_PFC_CAPS_SHIFT 8
+#define DCBX_PFC_CAPS_OFFSET 8
#define DCBX_PFC_MBC_MASK 0x00004000
-#define DCBX_PFC_MBC_SHIFT 14
+#define DCBX_PFC_MBC_OFFSET 14
#define DCBX_PFC_WILLING_MASK 0x00008000
-#define DCBX_PFC_WILLING_SHIFT 15
+#define DCBX_PFC_WILLING_OFFSET 15
#define DCBX_PFC_ENABLED_MASK 0x00010000
-#define DCBX_PFC_ENABLED_SHIFT 16
+#define DCBX_PFC_ENABLED_OFFSET 16
#define DCBX_PFC_ERROR_MASK 0x00020000
-#define DCBX_PFC_ERROR_SHIFT 17
+#define DCBX_PFC_ERROR_OFFSET 17
/* APP feature */
struct dcbx_app_priority_feature app;
@@ -436,7 +436,7 @@ struct dcbx_features {
struct dcbx_local_params {
u32 config;
#define DCBX_CONFIG_VERSION_MASK 0x00000007
-#define DCBX_CONFIG_VERSION_SHIFT 0
+#define DCBX_CONFIG_VERSION_OFFSET 0
#define DCBX_CONFIG_VERSION_DISABLED 0
#define DCBX_CONFIG_VERSION_IEEE 1
#define DCBX_CONFIG_VERSION_CEE 2
@@ -451,7 +451,7 @@ struct dcbx_mib {
u32 flags;
/*
#define DCBX_CONFIG_VERSION_MASK 0x00000007
- #define DCBX_CONFIG_VERSION_SHIFT 0
+ #define DCBX_CONFIG_VERSION_OFFSET 0
#define DCBX_CONFIG_VERSION_DISABLED 0
#define DCBX_CONFIG_VERSION_IEEE 1
#define DCBX_CONFIG_VERSION_CEE 2
@@ -470,7 +470,7 @@ struct lldp_system_tlvs_buffer_s {
struct dcb_dscp_map {
u32 flags;
#define DCB_DSCP_ENABLE_MASK 0x1
-#define DCB_DSCP_ENABLE_SHIFT 0
+#define DCB_DSCP_ENABLE_OFFSET 0
#define DCB_DSCP_ENABLE 1
u32 dscp_pri_map[8];
};
@@ -502,12 +502,12 @@ struct public_global {
#define MDUMP_REASON_DUMP_AGED (1 << 2)
u32 ext_phy_upgrade_fw;
#define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff)
-#define EXT_PHY_FW_UPGRADE_STATUS_SHIFT (0)
+#define EXT_PHY_FW_UPGRADE_STATUS_OFFSET (0)
#define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1)
#define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2)
#define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3)
#define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000)
-#define EXT_PHY_FW_UPGRADE_TYPE_SHIFT (16)
+#define EXT_PHY_FW_UPGRADE_TYPE_OFFSET (16)
};
/**************************************/
@@ -557,9 +557,9 @@ struct public_path {
/* Reset on mcp reset, and incremented for eveny process kill event. */
u32 process_kill;
#define PROCESS_KILL_COUNTER_MASK 0x0000ffff
-#define PROCESS_KILL_COUNTER_SHIFT 0
+#define PROCESS_KILL_COUNTER_OFFSET 0
#define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
-#define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
+#define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16
#define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
};
@@ -713,13 +713,13 @@ struct public_port {
u32 fc_npiv_nvram_tbl_size;
u32 transceiver_data;
#define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
-#define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
+#define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
#define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
#define ETH_TRANSCEIVER_STATE_VALID 0x00000003
#define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
#define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00
-#define ETH_TRANSCEIVER_TYPE_SHIFT 0x00000008
+#define ETH_TRANSCEIVER_TYPE_OFFSET 0x00000008
#define ETH_TRANSCEIVER_TYPE_NONE 0x00000000
#define ETH_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF
/* 1G Passive copper cable */
@@ -785,12 +785,12 @@ struct public_port {
/* Shows the Local Device EEE capabilities */
#define EEE_LD_ADV_STATUS_MASK 0x000000f0
-#define EEE_LD_ADV_STATUS_SHIFT 4
+#define EEE_LD_ADV_STATUS_OFFSET 4
#define EEE_1G_ADV (1 << 1)
#define EEE_10G_ADV (1 << 2)
/* Same values as in EEE_LD_ADV, but for Link Parter */
#define EEE_LP_ADV_STATUS_MASK 0x00000f00
-#define EEE_LP_ADV_STATUS_SHIFT 8
+#define EEE_LP_ADV_STATUS_OFFSET 8
/* Supported speeds for EEE */
#define EEE_SUPPORTED_SPEED_MASK 0x0000f000
@@ -800,9 +800,9 @@ struct public_port {
u32 eee_remote; /* Used for EEE in LLDP */
#define EEE_REMOTE_TW_TX_MASK 0x0000ffff
-#define EEE_REMOTE_TW_TX_SHIFT 0
+#define EEE_REMOTE_TW_TX_OFFSET 0
#define EEE_REMOTE_TW_RX_MASK 0xffff0000
-#define EEE_REMOTE_TW_RX_SHIFT 16
+#define EEE_REMOTE_TW_RX_OFFSET 16
u32 module_info;
#define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF
@@ -852,11 +852,11 @@ struct public_func {
/* function 0 of each port cannot be hidden */
#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
#define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
-#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
+#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET 0x00000001
#define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
-#define FUNC_MF_CFG_PROTOCOL_SHIFT 4
+#define FUNC_MF_CFG_PROTOCOL_OFFSET 4
#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
@@ -866,10 +866,10 @@ struct public_func {
/* MINBW, MAXBW */
/* value range - 0..100, increments in 1 % */
#define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
-#define FUNC_MF_CFG_MIN_BW_SHIFT 8
+#define FUNC_MF_CFG_MIN_BW_OFFSET 8
#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
#define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
-#define FUNC_MF_CFG_MAX_BW_SHIFT 16
+#define FUNC_MF_CFG_MAX_BW_OFFSET 16
#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
u32 status;
@@ -877,7 +877,7 @@ struct public_func {
u32 mac_upper; /* MAC */
#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
-#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
+#define FUNC_MF_CFG_UPPERMAC_OFFSET 0
#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
u32 mac_lower;
#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
@@ -890,7 +890,7 @@ struct public_func {
u32 ovlan_stag; /* tags */
#define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
-#define FUNC_MF_CFG_OV_STAG_SHIFT 0
+#define FUNC_MF_CFG_OV_STAG_OFFSET 0
#define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
u32 pf_allocation; /* vf per pf */
@@ -907,29 +907,29 @@ struct public_func {
u32 drv_id;
#define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
-#define DRV_ID_PDA_COMP_VER_SHIFT 0
+#define DRV_ID_PDA_COMP_VER_OFFSET 0
#define LOAD_REQ_HSI_VERSION 2
#define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
-#define DRV_ID_MCP_HSI_VER_SHIFT 16
+#define DRV_ID_MCP_HSI_VER_OFFSET 16
#define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \
- DRV_ID_MCP_HSI_VER_SHIFT)
+ DRV_ID_MCP_HSI_VER_OFFSET)
#define DRV_ID_DRV_TYPE_MASK 0x7f000000
-#define DRV_ID_DRV_TYPE_SHIFT 24
-#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
-#define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
-#define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT)
-#define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT)
-#define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT)
-#define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT)
-#define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT)
-#define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT)
-#define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT)
+#define DRV_ID_DRV_TYPE_OFFSET 24
+#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_OFFSET)
+#define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_OFFSET)
+#define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_OFFSET)
+#define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_OFFSET)
+#define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_OFFSET)
+#define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_OFFSET)
+#define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_OFFSET)
+#define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_OFFSET)
+#define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_OFFSET)
#define DRV_ID_DRV_INIT_HW_MASK 0x80000000
-#define DRV_ID_DRV_INIT_HW_SHIFT 31
-#define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
+#define DRV_ID_DRV_INIT_HW_OFFSET 31
+#define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_OFFSET)
};
/**************************************/
@@ -1014,13 +1014,13 @@ struct ocbb_data_stc {
#define MFW_SENSOR_LOCATION_EXTERNAL 2
#define MFW_SENSOR_LOCATION_SFP 3
-#define SENSOR_LOCATION_SHIFT 0
+#define SENSOR_LOCATION_OFFSET 0
#define SENSOR_LOCATION_MASK 0x000000ff
-#define THRESHOLD_HIGH_SHIFT 8
+#define THRESHOLD_HIGH_OFFSET 8
#define THRESHOLD_HIGH_MASK 0x0000ff00
-#define CRITICAL_TEMPERATURE_SHIFT 16
+#define CRITICAL_TEMPERATURE_OFFSET 16
#define CRITICAL_TEMPERATURE_MASK 0x00ff0000
-#define CURRENT_TEMP_SHIFT 24
+#define CURRENT_TEMP_OFFSET 24
#define CURRENT_TEMP_MASK 0xff000000
struct temperature_status_stc {
u32 num_of_sensors;
@@ -1085,18 +1085,18 @@ struct load_req_stc {
u32 fw_ver;
u32 misc0;
#define LOAD_REQ_ROLE_MASK 0x000000FF
-#define LOAD_REQ_ROLE_SHIFT 0
+#define LOAD_REQ_ROLE_OFFSET 0
#define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
-#define LOAD_REQ_LOCK_TO_SHIFT 8
+#define LOAD_REQ_LOCK_TO_OFFSET 8
#define LOAD_REQ_LOCK_TO_DEFAULT 0
#define LOAD_REQ_LOCK_TO_NONE 255
#define LOAD_REQ_FORCE_MASK 0x000F0000
-#define LOAD_REQ_FORCE_SHIFT 16
+#define LOAD_REQ_FORCE_OFFSET 16
#define LOAD_REQ_FORCE_NONE 0
#define LOAD_REQ_FORCE_PF 1
#define LOAD_REQ_FORCE_ALL 2
#define LOAD_REQ_FLAGS0_MASK 0x00F00000
-#define LOAD_REQ_FLAGS0_SHIFT 20
+#define LOAD_REQ_FLAGS0_OFFSET 20
#define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
};
@@ -1106,11 +1106,11 @@ struct load_rsp_stc {
u32 fw_ver;
u32 misc0;
#define LOAD_RSP_ROLE_MASK 0x000000FF
-#define LOAD_RSP_ROLE_SHIFT 0
+#define LOAD_RSP_ROLE_OFFSET 0
#define LOAD_RSP_HSI_MASK 0x0000FF00
-#define LOAD_RSP_HSI_SHIFT 8
+#define LOAD_RSP_HSI_OFFSET 8
#define LOAD_RSP_FLAGS0_MASK 0x000F0000
-#define LOAD_RSP_FLAGS0_SHIFT 16
+#define LOAD_RSP_FLAGS0_OFFSET 16
#define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
};
@@ -1245,7 +1245,7 @@ struct public_drv_mb {
* [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN
*/
#define DRV_MSG_CODE_GET_VMAC 0x00120000
-#define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4
+#define DRV_MSG_CODE_VMAC_TYPE_OFFSET 4
#define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
#define DRV_MSG_CODE_VMAC_TYPE_MAC 1
#define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
@@ -1273,9 +1273,9 @@ struct public_drv_mb {
/* Set function BW, params[15:8] - min, params[7:0] - max */
#define DRV_MSG_CODE_SET_BW 0x00190000
#define BW_MAX_MASK 0x000000ff
-#define BW_MAX_SHIFT 0
+#define BW_MAX_OFFSET 0
#define BW_MIN_MASK 0x0000ff00
-#define BW_MIN_SHIFT 8
+#define BW_MIN_OFFSET 8
/* When param is set to 1, all parities will be masked(disabled). When params
* are set to 0, parities will be unmasked again.
@@ -1308,9 +1308,9 @@ struct public_drv_mb {
#define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
#define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
-#define RESOURCE_CMD_REQ_RESC_SHIFT 0
+#define RESOURCE_CMD_REQ_RESC_OFFSET 0
#define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
-#define RESOURCE_CMD_REQ_OPCODE_SHIFT 5
+#define RESOURCE_CMD_REQ_OPCODE_OFFSET 5
/* request resource ownership with default aging */
#define RESOURCE_OPCODE_REQ 1
/* request resource ownership without aging */
@@ -1321,12 +1321,12 @@ struct public_drv_mb {
/* force resource release */
#define RESOURCE_OPCODE_FORCE_RELEASE 5
#define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
-#define RESOURCE_CMD_REQ_AGE_SHIFT 8
+#define RESOURCE_CMD_REQ_AGE_OFFSET 8
#define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
-#define RESOURCE_CMD_RSP_OWNER_SHIFT 0
+#define RESOURCE_CMD_RSP_OWNER_OFFSET 0
#define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
-#define RESOURCE_CMD_RSP_OPCODE_SHIFT 8
+#define RESOURCE_CMD_RSP_OPCODE_OFFSET 8
/* resource is free and granted to requester */
#define RESOURCE_OPCODE_GNT 1
/* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15,
@@ -1373,11 +1373,11 @@ struct public_drv_mb {
#define DRV_MSG_CODE_EXT_PHY_READ 0x00280000
/* Value should be placed in union */
#define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000
-#define DRV_MB_PARAM_ADDR_SHIFT 0
+#define DRV_MB_PARAM_ADDR_OFFSET 0
#define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF
-#define DRV_MB_PARAM_DEVAD_SHIFT 16
+#define DRV_MB_PARAM_DEVAD_OFFSET 16
#define DRV_MB_PARAM_DEVAD_MASK 0x001F0000
-#define DRV_MB_PARAM_PORT_SHIFT 21
+#define DRV_MB_PARAM_PORT_OFFSET 21
#define DRV_MB_PARAM_PORT_MASK 0x00600000
#define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000
@@ -1404,44 +1404,44 @@ struct public_drv_mb {
/* LLDP / DCBX params*/
#define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
-#define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
+#define DRV_MB_PARAM_LLDP_SEND_OFFSET 0
#define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
-#define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1
+#define DRV_MB_PARAM_LLDP_AGENT_OFFSET 1
#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
-#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
+#define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET 3
#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
-#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
+#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0
#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
-#define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0
+#define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0
#define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
-#define DRV_MB_PARAM_NVM_LEN_SHIFT 24
+#define DRV_MB_PARAM_NVM_LEN_OFFSET 24
#define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
-#define DRV_MB_PARAM_PHY_ADDR_SHIFT 0
+#define DRV_MB_PARAM_PHY_ADDR_OFFSET 0
#define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
-#define DRV_MB_PARAM_PHY_LANE_SHIFT 16
+#define DRV_MB_PARAM_PHY_LANE_OFFSET 16
#define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
-#define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29
+#define DRV_MB_PARAM_PHY_SELECT_PORT_OFFSET 29
#define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
-#define DRV_MB_PARAM_PHY_PORT_SHIFT 30
+#define DRV_MB_PARAM_PHY_PORT_OFFSET 30
#define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
-#define DRV_MB_PARAM_PHYMOD_LANE_SHIFT 0
+#define DRV_MB_PARAM_PHYMOD_LANE_OFFSET 0
#define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF
-#define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT 8
+#define DRV_MB_PARAM_PHYMOD_SIZE_OFFSET 8
#define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00
/* configure vf MSIX params*/
-#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
+#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET 0
#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
-#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
+#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET 8
#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
/* OneView configuration parametres */
-#define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
+#define DRV_MB_PARAM_OV_CURR_CFG_OFFSET 0
#define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
#define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
#define DRV_MB_PARAM_OV_CURR_CFG_OS 1
@@ -1452,7 +1452,7 @@ struct public_drv_mb {
#define DRV_MB_PARAM_OV_CURR_CFG_DCI 6
#define DRV_MB_PARAM_OV_CURR_CFG_HII 7
-#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0
+#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET 0
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0)
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1)
@@ -1465,17 +1465,17 @@ struct public_drv_mb {
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6)
#define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0
-#define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0
+#define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET 0
#define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF
-#define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
+#define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET 0
#define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
#define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
#define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
#define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
#define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
-#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
+#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET 0
#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
/* Not Installed*/
@@ -1486,36 +1486,36 @@ struct public_drv_mb {
/* installed and active */
#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
-#define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
+#define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0
#define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
#define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
-#define DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT 0
+#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
#define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
-#define DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT 2
+#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2
#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC
-#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT 8
+#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8
#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00
-#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT 16
+#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16
#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000
-#define DRV_MB_PARAM_GPIO_NUMBER_SHIFT 0
+#define DRV_MB_PARAM_GPIO_NUMBER_OFFSET 0
#define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF
-#define DRV_MB_PARAM_GPIO_VALUE_SHIFT 16
+#define DRV_MB_PARAM_GPIO_VALUE_OFFSET 16
#define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000
-#define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT 16
+#define DRV_MB_PARAM_GPIO_DIRECTION_OFFSET 16
#define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000
-#define DRV_MB_PARAM_GPIO_CTRL_SHIFT 24
+#define DRV_MB_PARAM_GPIO_CTRL_OFFSET 24
#define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000
/* Resource Allocation params - Driver version support*/
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
-#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
+#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
-#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
+#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0
#define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
@@ -1528,19 +1528,19 @@ struct public_drv_mb {
#define DRV_MB_PARAM_BIST_RC_FAILED 2
#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
-#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
+#define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET 0
#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
-#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
+#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET 8
#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF
-#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SHIFT 0
+#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
/* driver supports SmartLinQ parameter */
#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001
/* driver supports EEE parameter */
#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000
-#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_SHIFT 16
+#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET 16
u32 fw_mb_header;
#define FW_MSG_CODE_MASK 0xffff0000
@@ -1654,9 +1654,9 @@ struct public_drv_mb {
u32 fw_mb_param;
/* Resource Allocation params - MFW version support */
#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
-#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
+#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16
#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
-#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
+#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0
/* get MFW feature support response */
/* MFW supports SmartLinQ */
--
1.7.10.3
next prev parent reply other threads:[~2017-09-19 1:31 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-19 1:29 [PATCH 00/53] net/qede/base: update PMD to 2.6.0.1 Rasesh Mody
2017-09-19 1:29 ` [PATCH 01/53] net/qede/base: add NVM config options Rasesh Mody
2017-09-19 1:29 ` [PATCH 02/53] net/qede/base: update management FW supported features Rasesh Mody
2017-09-19 1:29 ` [PATCH 03/53] net/qede/base: use crc32 OSAL macro Rasesh Mody
2017-09-19 1:29 ` [PATCH 04/53] net/qede/base: allocate VF queues before PF Rasesh Mody
2017-09-19 1:29 ` [PATCH 05/53] net/qede/base: convert device type to enum Rasesh Mody
2017-09-19 1:29 ` [PATCH 06/53] net/qede/base: changes for VF queue zone Rasesh Mody
2017-09-19 1:29 ` [PATCH 07/53] net/qede/base: interchangeably use SB between PF and VF Rasesh Mody
2017-09-19 1:29 ` [PATCH 08/53] net/qede/base: add API to configure coalescing for VF queues Rasesh Mody
2017-09-19 1:29 ` [PATCH 09/53] net/qede/base: restrict cache line size register padding Rasesh Mody
2017-09-19 1:29 ` [PATCH 10/53] net/qede/base: fix to use a passed ptt handle Rasesh Mody
2017-09-19 1:29 ` [PATCH 11/53] net/qede/base: add a sanity check Rasesh Mody
2017-09-19 1:29 ` [PATCH 12/53] net/qede/base: add SmartAN support Rasesh Mody
2017-09-19 1:29 ` [PATCH 13/53] net/qede/base: alter driver's force load behavior Rasesh Mody
2017-09-19 1:29 ` [PATCH 14/53] net/qede/base: add mdump sub-commands Rasesh Mody
2017-09-19 1:29 ` [PATCH 15/53] net/qede/base: add EEE support Rasesh Mody
2017-09-19 1:29 ` [PATCH 16/53] net/qede/base: use passed ptt handler Rasesh Mody
2017-09-19 1:29 ` [PATCH 17/53] net/qede/base: prevent re-assertions of parity errors Rasesh Mody
2017-09-19 1:29 ` [PATCH 18/53] net/qede/base: avoid possible race condition Rasesh Mody
2017-09-19 1:29 ` [PATCH 19/53] net/qede/base: revise management FW mbox access scheme Rasesh Mody
2017-09-19 1:30 ` [PATCH 20/53] net/qede/base: remove helper functions/structures Rasesh Mody
2017-09-19 1:30 ` [PATCH 21/53] net/qede/base: initialize resc lock/unlock params Rasesh Mody
2017-09-19 1:30 ` Rasesh Mody [this message]
2017-09-19 1:30 ` [PATCH 23/53] net/qede/base: allow clients to override VF MSI-X table size Rasesh Mody
2017-09-19 1:30 ` [PATCH 24/53] net/qede/base: add API to send STAG config update to FW Rasesh Mody
2017-09-19 1:30 ` [PATCH 25/53] net/qede/base: add support for doorbell overflow recovery Rasesh Mody
2017-09-19 1:30 ` [PATCH 26/53] net/qede/base: block mbox command to unresponsive MFW Rasesh Mody
2017-09-19 1:30 ` [PATCH 27/53] net/qede/base: prevent stop vport assert by malicious VF Rasesh Mody
2017-09-19 1:30 ` [PATCH 28/53] net/qede/base: remove unused parameters Rasesh Mody
2017-09-19 1:30 ` [PATCH 29/53] net/qede/base: fix macros to check chip revision/metal Rasesh Mody
2017-09-20 11:00 ` [PATCH 00/53] net/qede/base: update PMD to 2.6.0.1 Ferruh Yigit
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1505784633-1171-23-git-send-email-rasesh.mody@cavium.com \
--to=rasesh.mody@cavium.com \
--cc=Dept-EngDPDKDev@cavium.com \
--cc=dev@dpdk.org \
--cc=ferruh.yigit@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.