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From: Rasesh Mody <rasesh.mody@cavium.com>
To: dev@dpdk.org, ferruh.yigit@intel.com
Cc: Rasesh Mody <rasesh.mody@cavium.com>, Dept-EngDPDKDev@cavium.com
Subject: [PATCH 46/53] net/qede/base: dcbx dscp related extensions
Date: Mon, 18 Sep 2017 18:51:36 -0700	[thread overview]
Message-ID: <1505785903-1741-17-git-send-email-rasesh.mody@cavium.com> (raw)
In-Reply-To: <1505785903-1741-1-git-send-email-rasesh.mody@cavium.com>

- Add an internal API ecore_dcbx_get_dscp_value() for getting the
dscp value for a given priority.

- Initialize dscp parameters in the dcbx-config cache to be used by
the clients for configuring dcbx parameters.

- Reset NIG_REG_DSCP_TO_TC_MAP_ENABLE register when user disables the dscp.

- Fix to always send "dscp + dcbx" update to FW.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
 drivers/net/qede/base/ecore_dcbx.c |  105 +++++++++++++++++++++---------------
 drivers/net/qede/base/ecore_dcbx.h |    5 ++
 2 files changed, 66 insertions(+), 44 deletions(-)

diff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c
index ba3560a..54c61bf 100644
--- a/drivers/net/qede/base/ecore_dcbx.c
+++ b/drivers/net/qede/base/ecore_dcbx.c
@@ -114,6 +114,21 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
 	}
 }
 
+u8 ecore_dcbx_get_dscp_value(struct ecore_hwfn *p_hwfn, u8 pri)
+{
+	struct ecore_dcbx_dscp_params *dscp = &p_hwfn->p_dcbx_info->get.dscp;
+	u8 i;
+
+	if (!dscp->enabled)
+		return ECORE_DCBX_DSCP_DISABLED;
+
+	for (i = 0; i < ECORE_DCBX_DSCP_SIZE; i++)
+		if (pri == dscp->dscp_pri_map[i])
+			return i;
+
+	return ECORE_DCBX_DSCP_DISABLED;
+}
+
 static void
 ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,
 		      struct ecore_hwfn *p_hwfn,
@@ -121,29 +136,18 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
 		      enum dcbx_protocol_type type,
 		      enum ecore_pci_personality personality)
 {
-	struct ecore_dcbx_dscp_params *dscp = &p_hwfn->p_dcbx_info->get.dscp;
-
 	/* PF update ramrod data */
 	p_data->arr[type].enable = enable;
 	p_data->arr[type].priority = prio;
 	p_data->arr[type].tc = tc;
-	p_data->arr[type].dscp_enable = dscp->enabled;
-	if (p_data->arr[type].dscp_enable) {
-		u8 i;
-
-		for (i = 0; i < ECORE_DCBX_DSCP_SIZE; i++)
-			if (prio == dscp->dscp_pri_map[i]) {
-				p_data->arr[type].dscp_val = i;
-				break;
-			}
+	p_data->arr[type].dscp_val = ecore_dcbx_get_dscp_value(p_hwfn, prio);
+	if (p_data->arr[type].dscp_val == ECORE_DCBX_DSCP_DISABLED) {
+		p_data->arr[type].dscp_enable = false;
+		p_data->arr[type].dscp_val = 0;
+	} else {
+		p_data->arr[type].dscp_enable = true;
 	}
-
-	if (enable && p_data->arr[type].dscp_enable)
-		p_data->arr[type].update = UPDATE_DCB_DSCP;
-	else if (enable)
-		p_data->arr[type].update = UPDATE_DCB;
-	else
-		p_data->arr[type].update = DONT_UPDATE_DCB_DSCP;
+	p_data->arr[type].update = UPDATE_DCB_DSCP;
 
 	/* QM reconf data */
 	if (p_hwfn->hw_info.personality == personality)
@@ -582,6 +586,31 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
 	params->remote.valid = true;
 }
 
+static void  ecore_dcbx_get_dscp_params(struct ecore_hwfn *p_hwfn,
+					struct ecore_dcbx_get *params)
+{
+	struct ecore_dcbx_dscp_params *p_dscp;
+	struct dcb_dscp_map *p_dscp_map;
+	int i, j, entry;
+	u32 pri_map;
+
+	p_dscp = &params->dscp;
+	p_dscp_map = &p_hwfn->p_dcbx_info->dscp_map;
+	p_dscp->enabled = GET_MFW_FIELD(p_dscp_map->flags, DCB_DSCP_ENABLE);
+
+	/* MFW encodes 64 dscp entries into 8 element array of u32 entries,
+	 * where each entry holds the 4bit priority map for 8 dscp entries.
+	 */
+	for (i = 0, entry = 0; i < ECORE_DCBX_DSCP_SIZE / 8; i++) {
+		pri_map = OSAL_BE32_TO_CPU(p_dscp_map->dscp_pri_map[i]);
+		DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "elem %d pri_map 0x%x\n",
+			   entry, pri_map);
+		for (j = 0; j < ECORE_DCBX_DSCP_SIZE / 8; j++, entry++)
+			p_dscp->dscp_pri_map[entry] = (u32)(pri_map >>
+							   (j * 4)) & 0xf;
+	}
+}
+
 static void
 ecore_dcbx_get_operational_params(struct ecore_hwfn *p_hwfn,
 				  struct ecore_dcbx_get *params)
@@ -640,31 +669,6 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
 	p_operational->valid = true;
 }
 
-static void  ecore_dcbx_get_dscp_params(struct ecore_hwfn *p_hwfn,
-					struct ecore_dcbx_get *params)
-{
-	struct ecore_dcbx_dscp_params *p_dscp;
-	struct dcb_dscp_map *p_dscp_map;
-	int i, j, entry;
-	u32 pri_map;
-
-	p_dscp = &params->dscp;
-	p_dscp_map = &p_hwfn->p_dcbx_info->dscp_map;
-	p_dscp->enabled = GET_MFW_FIELD(p_dscp_map->flags, DCB_DSCP_ENABLE);
-
-	/* MFW encodes 64 dscp entries into 8 element array of u32 entries,
-	 * where each entry holds the 4bit priority map for 8 dscp entries.
-	 */
-	for (i = 0, entry = 0; i < ECORE_DCBX_DSCP_SIZE / 8; i++) {
-		pri_map = OSAL_BE32_TO_CPU(p_dscp_map->dscp_pri_map[i]);
-		DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "elem %d pri_map 0x%x\n",
-			   entry, pri_map);
-		for (j = 0; j < ECORE_DCBX_DSCP_SIZE / 8; j++, entry++)
-			p_dscp->dscp_pri_map[entry] = (u32)(pri_map >>
-							   (j * 4)) & 0xf;
-	}
-}
-
 static void ecore_dcbx_get_local_lldp_params(struct ecore_hwfn *p_hwfn,
 					     struct ecore_dcbx_get *params)
 {
@@ -894,7 +898,9 @@ enum _ecore_status_t
 	/* Update the DSCP to TC mapping bit if required */
 	if ((type == ECORE_DCBX_OPERATIONAL_MIB) &&
 	    p_hwfn->p_dcbx_info->dscp_nig_update) {
-		ecore_wr(p_hwfn, p_ptt, NIG_REG_DSCP_TO_TC_MAP_ENABLE, 0x1);
+		u8 val = !!p_hwfn->p_dcbx_info->get.dscp.enabled;
+
+		ecore_wr(p_hwfn, p_ptt, NIG_REG_DSCP_TO_TC_MAP_ENABLE, val);
 		p_hwfn->p_dcbx_info->dscp_nig_update = false;
 	}
 
@@ -972,6 +978,8 @@ enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn,
 	if (rc != ECORE_SUCCESS)
 		goto out;
 
+	ecore_dcbx_get_dscp_params(p_hwfn, p_get);
+
 	rc = ecore_dcbx_get_params(p_hwfn, p_get, type);
 
 out:
@@ -1191,6 +1199,12 @@ enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn,
 	p_hwfn->p_dcbx_info->dscp_nig_update = true;
 
 	DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "flags = 0x%x\n", p_dscp_map->flags);
+	DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
+		   "pri_map[] = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+		   p_dscp_map->dscp_pri_map[0], p_dscp_map->dscp_pri_map[1],
+		   p_dscp_map->dscp_pri_map[2], p_dscp_map->dscp_pri_map[3],
+		   p_dscp_map->dscp_pri_map[4], p_dscp_map->dscp_pri_map[5],
+		   p_dscp_map->dscp_pri_map[6], p_dscp_map->dscp_pri_map[7]);
 
 	return ECORE_SUCCESS;
 }
@@ -1281,6 +1295,9 @@ enum _ecore_status_t ecore_dcbx_get_config_params(struct ecore_hwfn *p_hwfn,
 		p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_STATIC;
 
 	p_hwfn->p_dcbx_info->set.enabled = dcbx_info->operational.enabled;
+	OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set.dscp,
+		    &p_hwfn->p_dcbx_info->get.dscp,
+		    sizeof(struct ecore_dcbx_dscp_params));
 	OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set.config.params,
 		    &dcbx_info->operational.params,
 		    sizeof(p_hwfn->p_dcbx_info->set.config.params));
diff --git a/drivers/net/qede/base/ecore_dcbx.h b/drivers/net/qede/base/ecore_dcbx.h
index a42ebb4..5986245 100644
--- a/drivers/net/qede/base/ecore_dcbx.h
+++ b/drivers/net/qede/base/ecore_dcbx.h
@@ -17,6 +17,8 @@
 #include "ecore_hsi_common.h"
 #include "ecore_dcbx_api.h"
 
+#define ECORE_DCBX_DSCP_DISABLED 0XFF
+
 struct ecore_dcbx_info {
 	struct lldp_status_params_s lldp_remote[LLDP_MAX_LLDP_AGENTS];
 	struct lldp_config_params_s lldp_local[LLDP_MAX_LLDP_AGENTS];
@@ -52,4 +54,7 @@ enum _ecore_status_t
 void ecore_dcbx_set_pf_update_params(struct ecore_dcbx_results *p_src,
 				     struct pf_update_ramrod_data *p_dest);
 
+/* Returns TOS value for a given priority */
+u8 ecore_dcbx_get_dscp_value(struct ecore_hwfn *p_hwfn, u8 pri);
+
 #endif /* __ECORE_DCBX_H__ */
-- 
1.7.10.3

  parent reply	other threads:[~2017-09-19  1:52 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-19  1:51 [PATCH 30/53] net/qede/base: read per queue coalescing from HW Rasesh Mody
2017-09-19  1:51 ` [PATCH 31/53] net/qede/base: refactor device's number of ports logic Rasesh Mody
2017-09-19  1:51 ` [PATCH 32/53] net/qede/base: use proper units for rate limiting Rasesh Mody
2017-09-19  1:51 ` [PATCH 33/53] net/qede/base: use available macro Rasesh Mody
2017-09-19  1:51 ` [PATCH 34/53] net/qede/base: use function pointers for spq async callback Rasesh Mody
2017-09-19  1:51 ` [PATCH 35/53] net/qede/base: fix API return types Rasesh Mody
2017-09-19  1:51 ` [PATCH 36/53] net/qede/base: semantic changes Rasesh Mody
2017-09-19  1:51 ` [PATCH 37/53] net/qede/base: handle the error condition properly Rasesh Mody
2017-09-19  1:51 ` [PATCH 38/53] net/qede/base: add new macro for CMT mode Rasesh Mody
2017-09-19  1:51 ` [PATCH 39/53] net/qede/base: change verbosity Rasesh Mody
2017-09-19  1:51 ` [PATCH 40/53] net/qede/base: fix number of app table entries Rasesh Mody
2017-09-19  1:51 ` [PATCH 41/53] net/qede/base: update firmware to 8.30.12.0 Rasesh Mody
2017-09-19  1:51 ` [PATCH 42/53] net/qede/base: add UFP support Rasesh Mody
2017-09-19  1:51 ` [PATCH 43/53] net/qede/base: add support for mapped doorbell Bars for VFs Rasesh Mody
2017-09-19  1:51 ` [PATCH 44/53] net/qede/base: add support for driver attribute repository Rasesh Mody
2017-09-19  1:51 ` [PATCH 45/53] net/qede/base: move define to header file Rasesh Mody
2017-09-19  1:51 ` Rasesh Mody [this message]
2017-09-19  1:51 ` [PATCH 47/53] net/qede/base: add feature support for per-PF virtual link Rasesh Mody
2017-09-19  1:51 ` [PATCH 48/53] net/qede/base: catch an init command write failure Rasesh Mody
2017-09-19  1:51 ` [PATCH 49/53] net/qede/base: retain dcbx config till actually applied Rasesh Mody
2017-09-19  1:51 ` [PATCH 50/53] net/qede/base: disable aRFS for NPAR and 100G Rasesh Mody
2017-09-19  1:51 ` [PATCH 51/53] net/qede/base: add support for WoL writes Rasesh Mody
2017-09-19  1:51 ` [PATCH 52/53] net/qede/base: remove unused input parameter Rasesh Mody
2017-09-19  1:51 ` [PATCH 53/53] net/qede/base: update PMD version to 2.6.0.1 Rasesh Mody

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