All of lore.kernel.org
 help / color / mirror / Atom feed
From: chin.liang.see at intel.com <chin.liang.see@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 08/14] arm: socfpga: stratix10: Add MMU support for Stratix10 SoC
Date: Tue, 19 Sep 2017 17:22:25 +0800	[thread overview]
Message-ID: <1505812951-25088-9-git-send-email-chin.liang.see@intel.com> (raw)
In-Reply-To: <1505812951-25088-1-git-send-email-chin.liang.see@intel.com>

From: Chin Liang See <chin.liang.see@intel.com>

Add MMU support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
---
 arch/arm/mach-socfpga/Makefile        |  1 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 43e18d2..098e5e9 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
 obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
+obj-y	+= mmu-arm64_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o
 obj-y	+= wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
new file mode 100644
index 0000000..91c7f2e
--- /dev/null
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region socfpga_stratix10_mem_map[] = {
+	{
+		/* MEM 2GB*/
+		.virt	= 0x0UL,
+		.phys	= 0x0UL,
+		.size	= 0x80000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* FPGA 1.5GB */
+		.virt	= 0x80000000UL,
+		.phys	= 0x80000000UL,
+		.size	= 0x60000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* DEVICE 142MB */
+		.virt	= 0xF7000000UL,
+		.phys	= 0xF7000000UL,
+		.size	= 0x08E00000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* OCRAM 1MB but available 256KB */
+		.virt	= 0xFFE00000UL,
+		.phys	= 0xFFE00000UL,
+		.size	= 0x00100000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* DEVICE 32KB */
+		.virt	= 0xFFFC0000UL,
+		.phys	= 0xFFFC0000UL,
+		.size	= 0x00008000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* MEM 124GB */
+		.virt	= 0x0100000000UL,
+		.phys	= 0x0100000000UL,
+		.size	= 0x1F00000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* DEVICE 4GB */
+		.virt	= 0x2000000000UL,
+		.phys	= 0x2000000000UL,
+		.size	= 0x0100000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* List terminator */
+	},
+};
+
+struct mm_region *mem_map = socfpga_stratix10_mem_map;
-- 
2.2.2

  parent reply	other threads:[~2017-09-19  9:22 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-19  9:22 [U-Boot] [PATCH 00/14] Enable Stratix10 SoC support chin.liang.see at intel.com
2017-09-19  9:22 ` [U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC chin.liang.see at intel.com
2017-09-19  9:51   ` Marek Vasut
2017-09-19 13:13     ` See, Chin Liang
2017-09-19  9:22 ` [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC chin.liang.see at intel.com
2017-09-26 21:34   ` Dinh Nguyen
2017-09-29 13:06     ` See, Chin Liang
2017-09-26 21:37   ` Dinh Nguyen
2017-09-29 13:07     ` See, Chin Liang
2017-09-19  9:22 ` [U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock Manager driver " chin.liang.see at intel.com
2017-09-26 22:04   ` Dinh Nguyen
2017-09-29 12:58     ` See, Chin Liang
2017-09-19  9:22 ` [U-Boot] [PATCH 04/14] arm: socfpga: stratix10: Add Reset " chin.liang.see at intel.com
2017-09-26 22:08   ` Dinh Nguyen
2017-09-29 12:53     ` See, Chin Liang
2017-10-02 14:10       ` Dinh Nguyen
2017-09-19  9:22 ` [U-Boot] [PATCH 05/14] arm: socfpga: stratix10: Add pinmux support " chin.liang.see at intel.com
2017-09-19  9:22 ` [U-Boot] [PATCH 06/14] arm: socfpga: stratix10: Add misc " chin.liang.see at intel.com
2017-09-26 22:46   ` Dinh Nguyen
2017-09-29 12:51     ` See, Chin Liang
2017-09-19  9:22 ` [U-Boot] [PATCH 07/14] arm: socfpga: stratix10: Add mailbox " chin.liang.see at intel.com
2017-09-19  9:22 ` chin.liang.see at intel.com [this message]
2017-09-19  9:22 ` [U-Boot] [PATCH 09/14] arm: socfpga: Restructure the SPL file chin.liang.see at intel.com
2017-09-19  9:22 ` [U-Boot] [PATCH 10/14] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC chin.liang.see at intel.com
2017-09-19  9:22 ` [U-Boot] [PATCH 11/14] arm: socfpga: stratix10: Add timer support " chin.liang.see at intel.com
2017-09-19  9:22 ` [U-Boot] [PATCH 12/14] ddr: altera: stratix10: Add DDR " chin.liang.see at intel.com
2017-09-19  9:22 ` [U-Boot] [PATCH 13/14] board: altera: stratix10: Add socdk board " chin.liang.see at intel.com
2017-09-19  9:22 ` [U-Boot] [PATCH 14/14] arm: socfpga: stratix10: Enable Stratix10 SoC build chin.liang.see at intel.com

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1505812951-25088-9-git-send-email-chin.liang.see@intel.com \
    --to=chin.liang.see@intel.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.