From mboxrd@z Thu Jan 1 00:00:00 1970 From: tien.fong.chee at intel.com Date: Mon, 25 Sep 2017 16:40:12 +0800 Subject: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 In-Reply-To: <1506328815-23733-1-git-send-email-tien.fong.chee@intel.com> References: <1506328815-23733-1-git-send-email-tien.fong.chee@intel.com> Message-ID: <1506328815-23733-17-git-send-email-tien.fong.chee@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Tien Fong Chee Enhance preloader header with both additional program length and program entry offset attributes, which offset is relative to the start of program header. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h index 22d9e7f..33c9368 100644 --- a/arch/arm/mach-socfpga/include/mach/boot0.h +++ b/arch/arm/mach-socfpga/include/mach/boot0.h @@ -11,8 +11,15 @@ .balignl 64,0xf33db33f; .word 0x1337c0d3; /* SoCFPGA preloader validation word */ - .word 0xc01df00d; /* Version, flags, length */ - .word 0xcafec0d3; /* Checksum, zero-pad */ + .word 0xc01df00d; /* Header length(2B),flags(1B),version(1B) */ +#ifndef CONFIG_TARGET_SOCFPGA_GEN5 + .word 0xfeedface; /* Program length(4B) */ + .word 0xf00dcafe; /* + * Program entry offset(4B),relative to + * the start of program header + */ +#endif + .word 0xcafec0d3; /* Simple checksum(2B),spare offset(2B) */ nop; b reset; /* SoCFPGA jumps here */ -- 2.2.0